From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754439AbbFOKtm (ORCPT ); Mon, 15 Jun 2015 06:49:42 -0400 Received: from mail-by2on0117.outbound.protection.outlook.com ([207.46.100.117]:32192 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754233AbbFOKtY (ORCPT ); Mon, 15 Jun 2015 06:49:24 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; amacapital.net; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NPZFE8-08-VZT-02 X-M-MSG: From: Huang Rui To: Borislav Petkov , Andy Lutomirski , Thomas Gleixner , Peter Zijlstra , Ingo Molnar , "Rafael J. Wysocki" , "Len Brown" , John Stultz , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Weisbecker?= CC: , , Fengguang Wu , Aaron Lu , Suravee Suthikulanit , Tony Li , Ken Xue , Huang Rui Subject: [PATCH v5 1/2] x86, mwaitt: add monitorx and mwaitx instruction Date: Mon, 15 Jun 2015 18:48:03 +0800 Message-ID: <1434365284-1495-2-git-send-email-ray.huang@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1434365284-1495-1-git-send-email-ray.huang@amd.com> References: <1434365284-1495-1-git-send-email-ray.huang@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BN1AFFO11FD023;1:trIu2QkBYN4jg0mqXqXMl2oA6IX3tXfJVDlXWWJl2KIzz2tiIsKHQrsPOGZHM0uYjAyUFRmuu2uNZST5DXB1tApMXI9BEZNKfqP3WQk7a2pQbfSab3z/EAiaFM3w4/nZNql6it8HBjn73l9rqEo+aY9W+9oweLZSRwTx2rh4LVamAYtXSNY99Y+As9jztcJUdIc6JKIh7KULlpz3LrAWtZtlSIu05R0Ir92PaoEhAfi8H1LYBCii08Ez3V4PkiIv4XIxadAAsfOT5O2Xhpd8vlfY+5S9uK6lS4c1tRlKXmjavZdKv4XczC8dS1hJU6S84rbkSJYudD7d+yC4DIur3N9huhZ68Pjay3gP/Ax9rWc= X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(189002)(199003)(5003600100002)(87936001)(86362001)(575784001)(2950100001)(36756003)(77096005)(47776003)(77156002)(62966003)(48376002)(189998001)(5001770100001)(106466001)(105586002)(50226001)(101416001)(53416004)(50466002)(229853001)(46102003)(50986999)(19580405001)(92566002)(19580395003)(76176999)(33646002);DIR:OUT;SFP:1102;SCL:1;SRVR:BN3PR02MB1109;H:atltwp02.amd.com;FPR:;SPF:None;MLV:sfv;MX:1;A:1;LANG:en; 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MWAITT, another name is MWAITX (MWAIT with extensions), has a configurable timer that causes MWAITX to exit on expiration. Compared with MONITOR/MWAIT, there are minor differences in opcode and input parameters. MWAITX ECX[1]: enable timer if set MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks MWAIT MWAITX opcode 0f 01 c9 | 0f 01 fb ECX[0] value of RFLAGS.IF seen by instruction ECX[1] unused/#GP if set | enable timer if set ECX[31:2] unused/#GP if set EAX unused (reserve for hint) EBX[31:0] unused | max wait time (loops) MONITOR MONITORX opcode 0f 01 c8 | 0f 01 fa EAX (logical) address to monitor ECX #GP if not zero The software P0 frequency is the same as the TSC frequency. Max timeout = EBX/(TSC frequency) Signed-off-by: Huang Rui --- arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/mwait.h | 40 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..3ef1f6e 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -176,6 +176,7 @@ #define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */ #define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */ #define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */ +#define X86_FEATURE_MWAITT ( 6*32+29) /* Mwait extension (MonitorX/MwaitX) */ /* * Auxiliary flags: Linux defined - For features scattered in various diff --git a/arch/x86/include/asm/mwait.h b/arch/x86/include/asm/mwait.h index 653dfa7..1fbc89d 100644 --- a/arch/x86/include/asm/mwait.h +++ b/arch/x86/include/asm/mwait.h @@ -23,6 +23,14 @@ static inline void __monitor(const void *eax, unsigned long ecx, :: "a" (eax), "c" (ecx), "d"(edx)); } +static inline void __monitorx(const void *eax, unsigned long ecx, + unsigned long edx) +{ + /* "monitorx %eax, %ecx, %edx;" */ + asm volatile(".byte 0x0f, 0x01, 0xfa;" + :: "a" (eax), "c" (ecx), "d"(edx)); +} + static inline void __mwait(unsigned long eax, unsigned long ecx) { /* "mwait %eax, %ecx;" */ @@ -30,6 +38,38 @@ static inline void __mwait(unsigned long eax, unsigned long ecx) :: "a" (eax), "c" (ecx)); } +/* + * MWAITT allows for both a timer value to get you out of the MWAIT as + * well as the normal exit conditions. + * + * MWAITX ECX[1]: enable timer if set + * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks + * + * Below is the compared data between MWAIT and MWAITX on AMD + * processors: + * MWAIT MWAITX + * opcode 0f 01 c9 | 0f 01 fb + * ECX[0] value of RFLAGS.IF seen by instruction + * ECX[1] unused/#GP if set | enable timer if set + * ECX[31:2] unused/#GP if set + * EAX unused (reserve for hint) + * EBX[31:0] unused | max wait time (loops) + * + * MONITOR MONITORX + * opcode 0f 01 c8 | 0f 01 fa + * EAX (logical) address to monitor + * ECX #GP if not zero + * + * The software P0 frequency is the same as the TSC frequency. + */ +static inline void __mwaitx(unsigned long eax, unsigned long ebx, + unsigned long ecx) +{ + /* "mwaitx %eax, %ebx, %ecx;" */ + asm volatile(".byte 0x0f, 0x01, 0xfb;" + :: "a" (eax), "b" (ebx), "c" (ecx)); +} + static inline void __sti_mwait(unsigned long eax, unsigned long ecx) { trace_hardirqs_on(); -- 1.9.1