From: Keerthy <j-keerthy@ti.com>
To: <linux-omap@vger.kernel.org>
Cc: <galak@codeaurora.org>, <tony@atomide.com>, <t-kristo@ti.com>,
<pawel.moll@arm.com>, <linux-kernel@vger.kernel.org>,
<bcousson@baylibre.com>, <linux-clk@vger.kernel.org>,
<j-keerthy@ti.com>
Subject: [PATCH 2/2] ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock
Date: Thu, 18 Jun 2015 13:31:13 +0530 [thread overview]
Message-ID: <1434614473-8500-3-git-send-email-j-keerthy@ti.com> (raw)
In-Reply-To: <1434614473-8500-1-git-send-email-j-keerthy@ti.com>
cpsw needs the clock to be running at 50MHz in kernel. Hence setting
the default rate.
Signed-off-by: Keerthy <j-keerthy@ti.com>
---
arch/arm/boot/dts/am4372.dtsi | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index c80a3e2..1680602 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -521,8 +521,11 @@
#address-cells = <1>;
#size-cells = <1>;
ti,hwmods = "cpgmac0";
- clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
- clock-names = "fck", "cpts";
+ clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
+ <&dpll_clksel_mac_clk>;
+ clock-names = "fck", "cpts", "50mclk";
+ assigned-clocks = <&dpll_clksel_mac_clk>;
+ assigned-clock-rates = <50000000>;
status = "disabled";
cpdma_channels = <8>;
ale_entries = <1024>;
--
1.9.1
next prev parent reply other threads:[~2015-06-18 8:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-18 8:01 [PATCH 0/2] CLK: TI: add dpll_clksel_mac_clk node Keerthy
2015-06-18 8:01 ` [PATCH 1/2] CLK: TI: AM437X: " Keerthy
2015-06-18 8:01 ` Keerthy [this message]
2015-06-18 9:06 ` [PATCH 0/2] CLK: TI: " Mugunthan V N
2015-06-25 13:46 ` Keerthy
2015-07-14 11:06 ` Tony Lindgren
2015-07-14 13:28 ` Tero Kristo
2015-07-15 5:13 ` Tony Lindgren
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