From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753029AbbGARgw (ORCPT ); Wed, 1 Jul 2015 13:36:52 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:38337 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753014AbbGARgp (ORCPT ); Wed, 1 Jul 2015 13:36:45 -0400 From: Vitaly Andrianov To: , , , CC: Vitaly Andrianov Subject: [Resend PATCH] gpio/davinci: add interrupt support for GPIOs 16-31 Date: Wed, 1 Jul 2015 13:41:20 -0400 Message-ID: <1435772480-928-1-git-send-email-vitalya@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Interrupts for GPIOs 16 through 31 are enabled by bit 1 in the "binten" register (offset 8). Previous versions of GPIO only used bit 0, which enables GPIO 0-15 interrupts. Signed-off-by: Vitaly Andrianov --- I posted this patch on 06/18/15 and didn't get any response. Please, could you review the patch. drivers/gpio/gpio-davinci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index c5e05c8..c90629f 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -546,6 +546,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) chips[0].gpio_irq = bank_irq; chips[0].gpio_unbanked = pdata->gpio_unbanked; binten = BIT(0); + if (pdata->gpio_unbanked > 16) + binten |= BIT(1); /* AINTC handles mask/unmask; GPIO handles triggering */ irq = bank_irq; -- 1.9.1