From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753713AbbGIQo1 (ORCPT ); Thu, 9 Jul 2015 12:44:27 -0400 Received: from mga02.intel.com ([134.134.136.20]:29966 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753458AbbGIQoB (ORCPT ); Thu, 9 Jul 2015 12:44:01 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,441,1432623600"; d="scan'208";a="521479756" From: Andy Shevchenko To: linux-kernel@vger.kernel.org, Sascha Hauer , Peter De Schrijver , Tero Kristo , Stephen Boyd , Russell King , Dinh Nguyen Cc: Andy Shevchenko Subject: [PATCH v4 5/6] clk: tegra: switch to GENMASK() Date: Thu, 9 Jul 2015 19:43:53 +0300 Message-Id: <1436460234-61425-6-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436460234-61425-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1436460234-61425-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the code to use GENMASK() helper instead of div_mask() macro. Signed-off-by: Andy Shevchenko --- drivers/clk/tegra/clk-divider.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 59a5714..bf7f667 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -24,9 +24,8 @@ #include "clk.h" #define pll_out_override(p) (BIT((p->shift - 6))) -#define div_mask(d) ((1 << (d->width)) - 1) #define get_mul(d) (1 << d->frac_width) -#define get_max_div(d) div_mask(d) +#define get_max_div(d) GENMASK(d->width - 1, 0) #define PERIPH_CLK_UART_DIV_ENB BIT(24) @@ -73,7 +72,7 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw, u64 rate = parent_rate; reg = readl_relaxed(divider->reg) >> divider->shift; - div = reg & div_mask(divider); + div = reg & GENMASK(divider->width - 1, 0); mul = get_mul(divider); div += mul; @@ -120,7 +119,7 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, spin_lock_irqsave(divider->lock, flags); val = readl_relaxed(divider->reg); - val &= ~(div_mask(divider) << divider->shift); + val &= ~(GENMASK(divider->width - 1, 0) << divider->shift); val |= div << divider->shift; if (divider->flags & TEGRA_DIVIDER_UART) { -- 2.1.4