From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754121AbbGJIkN (ORCPT ); Fri, 10 Jul 2015 04:40:13 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:53245 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753316AbbGJIjz (ORCPT ); Fri, 10 Jul 2015 04:39:55 -0400 X-Listener-Flag: 11101 From: James Liao To: Matthias Brugger , Mike Turquette , Stephen Boyd , Heiko Stubner CC: , Daniel Kurtz , Ricky Liang , Rob Herring , Sascha Hauer , , , , , James Liao Subject: [PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings Date: Fri, 10 Jul 2015 16:39:33 +0800 Message-ID: <1436517574-17895-3-git-send-email-jamesjj.liao@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1436517574-17895-1-git-send-email-jamesjj.liao@mediatek.com> References: <1436517574-17895-1-git-send-email-jamesjj.liao@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Avoid u32 overflow when calculate post divider setting, and increase the max post divider setting from 3 (/8) to 4 (/16). Signed-off-by: James Liao --- drivers/clk/mediatek/clk-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 68af518..0e3f4ef 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -144,9 +144,9 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, if (freq > pll->data->fmax) freq = pll->data->fmax; - for (val = 0; val < 4; val++) { + for (val = 0; val < 5; val++) { *postdiv = 1 << val; - if (freq * *postdiv >= fmin) + if ((u64)freq * *postdiv >= fmin) break; } -- 1.8.1.1.dirty