[PATCH 2/3] perf/x86/intel/pt: Add an option to not force PSB+ on every schedule-in

[Alexander Shishkin <alexander.shishkin@linux.intel.com>]

Currently, the PT driver zeroes out the status register every time before
starting the event. However, all the writable bits are already taken care
of in pt_handle_status() function, except the new PacketByteCnt field,
which in new versions of PT contains the number of packet bytes written
since the last sync (PSB) packet. Zeroing it out before enabling PT forces
a sync packet to be written. This means that, with the existing code, a
sync packet (PSB and PSBEND, 18 bytes in total) will be generated every
time a PT event is scheduled in.

To avoid these unnecessary syncs and save a WRMSR in the fast path, this
patch adds a new attribute config bit "no_force_psb", which will disable
this zeroing WRMSR.

One exception where we do need to force PSB like this when tracing starts,
so that the decoder has a clear sync point in the trace. For this purpose
we aready have hw::itrace_started flag, which we are currently using to
output PERF_RECORD_ITRACE_START. This patch moves setting itrace_started
from perf core to the pmu::start, where it should still be 0 on the very
first run.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
---
 arch/x86/kernel/cpu/perf_event.h          |  1 +
 arch/x86/kernel/cpu/perf_event_intel_pt.c | 22 ++++++++++++++++++++--
 kernel/events/core.c                      |  2 --
 3 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 3474cf26b6..d7aa6c5630 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -77,6 +77,7 @@ struct event_constraint {
 #define PERF_X86_EVENT_EXCL_ACCT	0x0200 /* accounted EXCL event */
 #define PERF_X86_EVENT_AUTO_RELOAD	0x0400 /* use PEBS auto-reload */
 #define PERF_X86_EVENT_FREERUNNING	0x0800 /* use freerunning PEBS */
+#define PERF_X86_EVENT_PT_NO_FORCE_PSB	0x1000 /* don't force PSB+ packets */
 
 
 struct amd_nb {
diff --git a/arch/x86/kernel/cpu/perf_event_intel_pt.c b/arch/x86/kernel/cpu/perf_event_intel_pt.c
index aacd3c9bed..6c40455cd1 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_pt.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_pt.c
@@ -100,6 +100,7 @@ static struct attribute_group pt_cap_group = {
 	.name	= "caps",
 };
 
+PMU_FORMAT_ATTR(no_force_psb,	"config:0"	);
 PMU_FORMAT_ATTR(cyc,		"config:1"	);
 PMU_FORMAT_ATTR(mtc,		"config:9"	);
 PMU_FORMAT_ATTR(tsc,		"config:10"	);
@@ -109,6 +110,7 @@ PMU_FORMAT_ATTR(cyc_thresh,	"config:19-22"	);
 PMU_FORMAT_ATTR(psb_period,	"config:24-27"	);
 
 static struct attribute *pt_formats_attr[] = {
+	&format_attr_no_force_psb.attr,
 	&format_attr_cyc.attr,
 	&format_attr_mtc.attr,
 	&format_attr_tsc.attr,
@@ -199,6 +201,18 @@ static bool pt_event_valid(struct perf_event *event)
 	u64 config = event->attr.config;
 	u64 allowed, requested;
 
+	/*
+	 * Re-use one of the config bits to enable resetting packet byte
+	 * count that will result in outputting PSB+ at every event enable.
+	 * Since we don't allow setting bit 0 (TraceEn) directly from
+	 * attr::config, we can re-use it for our purpose.
+	 */
+	if (config & BIT(0)) {
+		event->hw.flags |= PERF_X86_EVENT_PT_NO_FORCE_PSB;
+		event->attr.config &= ~BIT(0);
+		config = event->attr.config;
+	}
+
 	if ((config & PT_CONFIG_MASK) != config)
 		return false;
 
@@ -245,6 +259,12 @@ static void pt_config(struct perf_event *event)
 {
 	u64 reg;
 
+	if (!(event->hw.flags & PERF_X86_EVENT_PT_NO_FORCE_PSB) ||
+	    !(event->hw.itrace_started)) {
+		event->hw.itrace_started = 1;
+		wrmsrl(MSR_IA32_RTIT_STATUS, 0);
+	}
+
 	reg = RTIT_CTL_TOPA | RTIT_CTL_BRANCH_EN | RTIT_CTL_TRACEEN;
 
 	if (!event->attr.exclude_kernel)
@@ -964,7 +984,6 @@ void intel_pt_interrupt(void)
 
 		pt_config_buffer(buf->cur->table, buf->cur_idx,
 				 buf->output_off);
-		wrmsrl(MSR_IA32_RTIT_STATUS, 0);
 		pt_config(event);
 	}
 }
@@ -988,7 +1007,6 @@ static void pt_event_start(struct perf_event *event, int mode)
 
 	pt_config_buffer(buf->cur->table, buf->cur_idx,
 			 buf->output_off);
-	wrmsrl(MSR_IA32_RTIT_STATUS, 0);
 	pt_config(event);
 }
 
diff --git a/kernel/events/core.c b/kernel/events/core.c
index d3dae3419b..15da13237a 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -6040,8 +6040,6 @@ static void perf_log_itrace_start(struct perf_event *event)
 	    event->hw.itrace_started)
 		return;
 
-	event->hw.itrace_started = 1;
-
 	rec.header.type	= PERF_RECORD_ITRACE_START;
 	rec.header.misc	= 0;
 	rec.header.size	= sizeof(rec);
-- 
2.1.4