From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1945922AbbGQNri (ORCPT ); Fri, 17 Jul 2015 09:47:38 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:33219 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758324AbbGQNrg (ORCPT ); Fri, 17 Jul 2015 09:47:36 -0400 From: Roger Quadros To: , CC: , , , , , , , Roger Quadros Subject: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY Date: Fri, 17 Jul 2015 16:47:23 +0300 Message-ID: <1437140844-6032-3-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1437140844-6032-1-git-send-email-rogerq@ti.com> References: <1437140844-6032-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This register is required to be passed to the SATA PHY driver to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock). Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 8f1e25b..4a0718c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1140,6 +1140,7 @@ ctrl-module = <&omap_control_sata>; clocks = <&sys_clkin1>, <&sata_ref_clk>; clock-names = "sysclk", "refclk"; + syscon-pllreset = <&scm_conf 0x3fc>; #phy-cells = <0>; }; -- 2.1.4