From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756657AbbGTQhL (ORCPT ); Mon, 20 Jul 2015 12:37:11 -0400 Received: from mail-bl2on0074.outbound.protection.outlook.com ([65.55.169.74]:63598 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752644AbbGTQhI (ORCPT ); Mon, 20 Jul 2015 12:37:08 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.227) smtp.mailfrom=opensource.altera.com; lists.infradead.org; dkim=none (message not signed) header.d=none; Authentication-Results: arm.linux.org.uk; dkim=none (message not signed) header.d=none; From: To: CC: , , , Dinh Nguyen Subject: [PATCH] ARM: socfpga: add reset for the Arria 10 platform Date: Mon, 20 Jul 2015 11:30:53 -0500 Message-ID: <1437409853-29070-1-git-send-email-dinguyen@opensource.altera.com> X-Mailer: git-send-email 2.4.5 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: SN1PR0701CA0016.namprd07.prod.outlook.com (25.162.96.26) To BY1PR03MB1372.namprd03.prod.outlook.com (25.162.109.30) X-Microsoft-Exchange-Diagnostics-untrusted: 1;BY1PR03MB1372;2:yju3eVx1a/ov+G7lTZu04pyTC3z2EOSnNmCz3o0lmuecqH1d/Y0zUsSPubaCKF3m;3:mAgbe+a89pn1xAdEjj1Fm3f3r09nmv7s5HA0dliADahZdn+PgMjsSkpjIEbRv1/SuMewhuFYFOuxupFxuvFqAQ/8MXF4MNNAJdyxicUOWwkXCFnktEuZZL/SQxvy3RlT3/KXDnBh5k9iToZXvEmn2Q==;25:LukVsmD4MApDtTvgETQ5RrF2GOcBkvFpQ9UfzuH1A/hLLHkQu76ug/Af2NllHroDtktSODnfdx/+2cv3pJ39RgYhBgQgKYPEUK3SkUCUq6wRyFqxdsgtUFCfOrPYzaP/ANC+sh0nUaGIlzdVeXoqtGDY3jGvqCSR0Lql5Z2zfXi8qkPbHaSqQ4ULI0l2n+0wwkeZ1PTNOGE6YzaJVmIq+V5HeZysSmTwtIw5G6xVS5XrNVDrrAH2ssyNeYJABcRaOWyB5SxwGVBtFZDcLt2d0g==;20:gnza1PeCos+RZqbAwGBBaHM2TgRHpMcTlXU9mU0y7x9NOn4y4rEYEv3J9KwcXfg+pN2eU6y8KJe3g96f4EIA4Kc0WJWhqZgLcj2e3ksRVBjjbuSF8Grzu98VWnH7QxSMKU7YKjYPHuPjvQq6OdA9oV641d1SRsl9noo3a1c8exM= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR03MB1372;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR03MB1403;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB117; 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Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/core.h | 1 + arch/arm/mach-socfpga/socfpga.c | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 7259c37..5bc6ea8 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -25,6 +25,7 @@ #define SOCFPGA_RSTMGR_MODPERRST 0x14 #define SOCFPGA_RSTMGR_BRGMODRST 0x1c +#define SOCFPGA_A10_RSTMGR_CTRL 0xC #define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 /* System Manager bits */ diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 19643a7..48c82af 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -74,6 +74,19 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); } +static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd) +{ + u32 temp; + + temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); + + if (mode == REBOOT_HARD) + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; + else + temp |= RSTMGR_CTRL_SWWARMRSTREQ; + writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); +} + static const char *altera_dt_match[] = { "altr,socfpga", NULL @@ -86,3 +99,16 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA") .restart = socfpga_cyclone5_restart, .dt_compat = altera_dt_match, MACHINE_END + +static const char *altera_a10_dt_match[] = { + "altr,socfpga-arria10", + NULL +}; + +DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, + .init_irq = socfpga_init_irq, + .restart = socfpga_arria10_restart, + .dt_compat = altera_dt_match, +MACHINE_END -- 2.4.5