From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965525AbbHKP54 (ORCPT ); Tue, 11 Aug 2015 11:57:56 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:40557 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965508AbbHKP5v (ORCPT ); Tue, 11 Aug 2015 11:57:51 -0400 From: Kishon Vijay Abraham I To: CC: , Subject: [PATCH 19/19] phy: lpc18xx-usb-otg: fix clock order in phy init Date: Tue, 11 Aug 2015 21:27:18 +0530 Message-ID: <1439308638-14582-20-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1439308638-14582-1-git-send-email-kishon@ti.com> References: <1439308638-14582-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joachim Eastwood Changing the frequency of the USB clock must be done before the PLL is powered on (prepared). This matters when the USB clock is not setup by either boot ROM or boot loader. Reorder the function calls to adhere to the order noted in the user manual. Signed-off-by: Joachim Eastwood Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-lpc18xx-usb-otg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/phy/phy-lpc18xx-usb-otg.c b/drivers/phy/phy-lpc18xx-usb-otg.c index 3aa8e4d..3b7a71e 100644 --- a/drivers/phy/phy-lpc18xx-usb-otg.c +++ b/drivers/phy/phy-lpc18xx-usb-otg.c @@ -33,12 +33,12 @@ static int lpc18xx_usb_otg_phy_init(struct phy *phy) struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy); int ret; - ret = clk_prepare(lpc->clk); + /* The PHY must be clocked at 480 MHz */ + ret = clk_set_rate(lpc->clk, 480000000); if (ret) return ret; - /* The PHY must be clocked at 480 MHz */ - return clk_set_rate(lpc->clk, 480000000); + return clk_prepare(lpc->clk); } static int lpc18xx_usb_otg_phy_exit(struct phy *phy) -- 1.7.9.5