From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751949AbbHQWdm (ORCPT ); Mon, 17 Aug 2015 18:33:42 -0400 Received: from mga09.intel.com ([134.134.136.24]:15658 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751282AbbHQWdl (ORCPT ); Mon, 17 Aug 2015 18:33:41 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,697,1432623600"; d="scan'208";a="785939915" Message-ID: <1439850820.21627.11.camel@schen9-desk2.jf.intel.com> Subject: Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations From: Tim Chen To: Dave Hansen Cc: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Herbert Xu , Chandramouli Narayanan , x86@kernel.org, linux-kernel@vger.kernel.org, Borislav Petkov , mouli_7982@yahoo.com Date: Mon, 17 Aug 2015 15:33:40 -0700 In-Reply-To: <55D24FEA.1000803@intel.com> References: <1439844283.21627.5.camel@schen9-desk2.jf.intel.com> <55D24FEA.1000803@intel.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.8.5 (3.8.5-2.fc19) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2015-08-17 at 14:19 -0700, Dave Hansen wrote: > On 08/17/2015 01:44 PM, Tim Chen wrote: > > @@ -401,6 +402,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; > > #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) > > #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT) > > #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT) > > +#define cpu_has_sha_ni boot_cpu_has(X86_FEATURE_SHA_NI) > > I think we're trying not to add these cpu_has_* macros any more. For > MPX at least we were encouraged to call cpu_has(X86_FEATURE_*) directly. > > In the patch description, it might also be nice to remind folks that > this will feature will also show up as "sha_ni" in /proc/cpuinfo. Okay, in that case, I've modified the patch to below: Tim --->8--- Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations To: Thomas Gleixner , Ingo Molnar , H. Peter Anvin Cc: Herbert Xu , Chandramouli Narayanan , x86@kernel.org, linux-kernel@vger.kernel.org The Intel Secure Hash Algorithm Extensions are designed to improve the performance of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit. This will allow the feature to be shown as sha_ni in the /proc/cpuinfo. The SHA extension programming guide is found in chapter 8 of the Intel Architecture Instruction Set Extensions Programming reference: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Signed-off-by: Chandramouli Narayanan Signed-off-by: Tim Chen --- arch/x86/include/asm/cpufeature.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 3d6606f..a94f83d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -239,6 +239,7 @@ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ -- 1.8.3.1