[PATCH -next] mips: Enable common clock framework for malta and sead3

[Guenter Roeck <linux@roeck-us.net>]

Since commit e69b3d70ac57 ("CLOCKSOURCE: mips-gic: Update clockevent
frequency on clock rate changes"), malta_defconfig and sead3_defconfig
fail to build as follows.

drivers/clocksource/mips-gic-timer.c: In function 'gic_clk_notifier':
drivers/clocksource/mips-gic-timer.c:102:16:
	error: 'POST_RATE_CHANGE' undeclared
drivers/clocksource/mips-gic-timer.c:103:48:
	error: dereferencing pointer to incomplete type
drivers/clocksource/mips-gic-timer.c: In function 'gic_clocksource_of_init':
drivers/clocksource/mips-gic-timer.c:209:3:
	error: implicit declaration of function 'clk_notifier_register'

Fix by enabling COMMON_CLK for both configurations. Build tested for
malta_defconfig and sead3_defconfig. Tested with qemu malta emulation.

Fixes: e69b3d70ac57 ("CLOCKSOURCE: mips-gic: Update clockevent frequency on clock rate changes")
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 arch/mips/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 09b8fe95aeb0..7af84b4d3269 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -409,6 +409,7 @@ config MIPS_MALTA
 	select CEVT_R4K
 	select CSRC_R4K
 	select CLKSRC_MIPS_GIC
+	select COMMON_CLK
 	select DMA_MAYBE_COHERENT
 	select GENERIC_ISA_DMA
 	select HAVE_PCSPKR_PLATFORM
@@ -459,6 +460,7 @@ config MIPS_SEAD3
 	select CEVT_R4K
 	select CSRC_R4K
 	select CLKSRC_MIPS_GIC
+	select COMMON_CLK
 	select CPU_MIPSR2_IRQ_VI
 	select CPU_MIPSR2_IRQ_EI
 	select DMA_NONCOHERENT
-- 
2.1.4