From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754701AbbIJEOZ (ORCPT ); Thu, 10 Sep 2015 00:14:25 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:35543 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750738AbbIJEOV (ORCPT ); Thu, 10 Sep 2015 00:14:21 -0400 From: Shraddha Barke To: Greg Kroah-Hartman , Lars-Peter Clausen , Jonathan Cameron , Peter Meerwald , Hartmut Knaack , linux-kernel@vger.kernel.org, Julia Lawall Cc: Shraddha Barke Subject: [PATCH 2/6] Staging: iio: cdc: ad7152.c: Prefer using the BIT macro Date: Thu, 10 Sep 2015 09:43:50 +0530 Message-Id: <1441858434-2846-2-git-send-email-shraddha.6596@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1441858434-2846-1-git-send-email-shraddha.6596@gmail.com> References: <1441858434-2846-1-git-send-email-shraddha.6596@gmail.com> X-Cyberoam-smtpxy-version: 1.0.6.3 X-Cyberoam-AV-Policy: default X-CTCH-PVer: 0000001 X-CTCH-Spam: Unknown X-CTCH-VOD: Unknown X-CTCH-Flags: 0 X-CTCH-RefID: str=0001.0A150202.55F10391.02AF,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0 X-CTCH-Score: 0.000 X-CTCH-ScoreCust: 0.000 X-CTCH-Rules: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch replaces bit shifting on 1 with the BIT(x) macro as it's extensively used by other function in this driver. This was done with coccinelle: @@ int g; @@ -(1 << g) +BIT(g) Signed-off-by: Shraddha Barke --- drivers/staging/iio/cdc/ad7152.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/staging/iio/cdc/ad7152.c b/drivers/staging/iio/cdc/ad7152.c index 87110d9..ba44c0e 100644 --- a/drivers/staging/iio/cdc/ad7152.c +++ b/drivers/staging/iio/cdc/ad7152.c @@ -41,30 +41,30 @@ #define AD7152_REG_CFG2 26 /* Status Register Bit Designations (AD7152_REG_STATUS) */ -#define AD7152_STATUS_RDY1 (1 << 0) -#define AD7152_STATUS_RDY2 (1 << 1) -#define AD7152_STATUS_C1C2 (1 << 2) -#define AD7152_STATUS_PWDN (1 << 7) +#define AD7152_STATUS_RDY1 BIT(0) +#define AD7152_STATUS_RDY2 BIT(1) +#define AD7152_STATUS_C1C2 BIT(2) +#define AD7152_STATUS_PWDN BIT(7) /* Setup Register Bit Designations (AD7152_REG_CHx_SETUP) */ -#define AD7152_SETUP_CAPDIFF (1 << 5) +#define AD7152_SETUP_CAPDIFF BIT(5) #define AD7152_SETUP_RANGE_2pF (0 << 6) -#define AD7152_SETUP_RANGE_0_5pF (1 << 6) +#define AD7152_SETUP_RANGE_0_5pF BIT(6) #define AD7152_SETUP_RANGE_1pF (2 << 6) #define AD7152_SETUP_RANGE_4pF (3 << 6) #define AD7152_SETUP_RANGE(x) ((x) << 6) /* Config Register Bit Designations (AD7152_REG_CFG) */ -#define AD7152_CONF_CH2EN (1 << 3) -#define AD7152_CONF_CH1EN (1 << 4) +#define AD7152_CONF_CH2EN BIT(3) +#define AD7152_CONF_CH1EN BIT(4) #define AD7152_CONF_MODE_IDLE (0 << 0) -#define AD7152_CONF_MODE_CONT_CONV (1 << 0) +#define AD7152_CONF_MODE_CONT_CONV BIT(0) #define AD7152_CONF_MODE_SINGLE_CONV (2 << 0) #define AD7152_CONF_MODE_OFFS_CAL (5 << 0) #define AD7152_CONF_MODE_GAIN_CAL (6 << 0) /* Capdac Register Bit Designations (AD7152_REG_CAPDAC_XXX) */ -#define AD7152_CAPDAC_DACEN (1 << 7) +#define AD7152_CAPDAC_DACEN BIT(7) #define AD7152_CAPDAC_DACP(x) ((x) & 0x1F) /* CFG2 Register Bit Designations (AD7152_REG_CFG2) */ -- 2.1.4