From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754776AbbIJEOj (ORCPT ); Thu, 10 Sep 2015 00:14:39 -0400 Received: from mail-pa0-f44.google.com ([209.85.220.44]:36805 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750738AbbIJEOd (ORCPT ); Thu, 10 Sep 2015 00:14:33 -0400 From: Shraddha Barke To: Greg Kroah-Hartman , Lars-Peter Clausen , Jonathan Cameron , Peter Meerwald , Hartmut Knaack , linux-kernel@vger.kernel.org, Julia Lawall Cc: Shraddha Barke Subject: [PATCH 4/6] Staging: iio: cdc: ad7746.c: Prefer using the BIT macro Date: Thu, 10 Sep 2015 09:43:52 +0530 Message-Id: <1441858434-2846-4-git-send-email-shraddha.6596@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1441858434-2846-1-git-send-email-shraddha.6596@gmail.com> References: <1441858434-2846-1-git-send-email-shraddha.6596@gmail.com> X-Cyberoam-smtpxy-version: 1.0.6.3 X-Cyberoam-AV-Policy: default X-CTCH-PVer: 0000001 X-CTCH-Spam: Unknown X-CTCH-VOD: Unknown X-CTCH-Flags: 0 X-CTCH-RefID: str=0001.0A150206.55F103A7.02DB,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0 X-CTCH-Score: 0.000 X-CTCH-ScoreCust: 0.000 X-CTCH-Rules: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch replaces bit shifting on 1 with the BIT(x) macro as it's extensively used by other function in this driver. This was done with coccinelle: @@ int g; @@ -(1 << g) +BIT(g) Signed-off-by: Shraddha Barke --- drivers/staging/iio/cdc/ad7746.c | 42 ++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/staging/iio/cdc/ad7746.c b/drivers/staging/iio/cdc/ad7746.c index e6e9eaa..e17d4e1 100644 --- a/drivers/staging/iio/cdc/ad7746.c +++ b/drivers/staging/iio/cdc/ad7746.c @@ -46,48 +46,48 @@ #define AD7746_REG_VOLT_GAINL 18 /* Status Register Bit Designations (AD7746_REG_STATUS) */ -#define AD7746_STATUS_EXCERR (1 << 3) -#define AD7746_STATUS_RDY (1 << 2) -#define AD7746_STATUS_RDYVT (1 << 1) -#define AD7746_STATUS_RDYCAP (1 << 0) +#define AD7746_STATUS_EXCERR BIT(3) +#define AD7746_STATUS_RDY BIT(2) +#define AD7746_STATUS_RDYVT BIT(1) +#define AD7746_STATUS_RDYCAP BIT(0) /* Capacitive Channel Setup Register Bit Designations (AD7746_REG_CAP_SETUP) */ -#define AD7746_CAPSETUP_CAPEN (1 << 7) -#define AD7746_CAPSETUP_CIN2 (1 << 6) /* AD7746 only */ -#define AD7746_CAPSETUP_CAPDIFF (1 << 5) -#define AD7746_CAPSETUP_CACHOP (1 << 0) +#define AD7746_CAPSETUP_CAPEN BIT(7) +#define AD7746_CAPSETUP_CIN2 BIT(6) /* AD7746 only */ +#define AD7746_CAPSETUP_CAPDIFF BIT(5) +#define AD7746_CAPSETUP_CACHOP BIT(0) /* Voltage/Temperature Setup Register Bit Designations (AD7746_REG_VT_SETUP) */ -#define AD7746_VTSETUP_VTEN (1 << 7) +#define AD7746_VTSETUP_VTEN BIT(7) #define AD7746_VTSETUP_VTMD_INT_TEMP (0 << 5) -#define AD7746_VTSETUP_VTMD_EXT_TEMP (1 << 5) +#define AD7746_VTSETUP_VTMD_EXT_TEMP BIT(5) #define AD7746_VTSETUP_VTMD_VDD_MON (2 << 5) #define AD7746_VTSETUP_VTMD_EXT_VIN (3 << 5) -#define AD7746_VTSETUP_EXTREF (1 << 4) -#define AD7746_VTSETUP_VTSHORT (1 << 1) -#define AD7746_VTSETUP_VTCHOP (1 << 0) +#define AD7746_VTSETUP_EXTREF BIT(4) +#define AD7746_VTSETUP_VTSHORT BIT(1) +#define AD7746_VTSETUP_VTCHOP BIT(0) /* Excitation Setup Register Bit Designations (AD7746_REG_EXC_SETUP) */ -#define AD7746_EXCSETUP_CLKCTRL (1 << 7) -#define AD7746_EXCSETUP_EXCON (1 << 6) -#define AD7746_EXCSETUP_EXCB (1 << 5) -#define AD7746_EXCSETUP_NEXCB (1 << 4) -#define AD7746_EXCSETUP_EXCA (1 << 3) -#define AD7746_EXCSETUP_NEXCA (1 << 2) +#define AD7746_EXCSETUP_CLKCTRL BIT(7) +#define AD7746_EXCSETUP_EXCON BIT(6) +#define AD7746_EXCSETUP_EXCB BIT(5) +#define AD7746_EXCSETUP_NEXCB BIT(4) +#define AD7746_EXCSETUP_EXCA BIT(3) +#define AD7746_EXCSETUP_NEXCA BIT(2) #define AD7746_EXCSETUP_EXCLVL(x) (((x) & 0x3) << 0) /* Config Register Bit Designations (AD7746_REG_CFG) */ #define AD7746_CONF_VTFS(x) ((x) << 6) #define AD7746_CONF_CAPFS(x) ((x) << 3) #define AD7746_CONF_MODE_IDLE (0 << 0) -#define AD7746_CONF_MODE_CONT_CONV (1 << 0) +#define AD7746_CONF_MODE_CONT_CONV BIT(0) #define AD7746_CONF_MODE_SINGLE_CONV (2 << 0) #define AD7746_CONF_MODE_PWRDN (3 << 0) #define AD7746_CONF_MODE_OFFS_CAL (5 << 0) #define AD7746_CONF_MODE_GAIN_CAL (6 << 0) /* CAPDAC Register Bit Designations (AD7746_REG_CAPDACx) */ -#define AD7746_CAPDAC_DACEN (1 << 7) +#define AD7746_CAPDAC_DACEN BIT(7) #define AD7746_CAPDAC_DACP(x) ((x) & 0x7F) /* -- 2.1.4