From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753606AbbIJJku (ORCPT ); Thu, 10 Sep 2015 05:40:50 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:48312 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753392AbbIJJkq (ORCPT ); Thu, 10 Sep 2015 05:40:46 -0400 Message-ID: <1441878044.3280.31.camel@pengutronix.de> Subject: Re: [RESEND PATCH 3/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC From: Philipp Zabel To: Chen Feng Cc: linux-kernel@vger.kernel.org, dan.zhao@hisilicon.com, w.f@huawei.com, haojian.zhuang@linaro.org, bintian.wang@huawei.com, devicetree@vger.kernel.org Date: Thu, 10 Sep 2015 11:40:44 +0200 In-Reply-To: <1441865490-104686-3-git-send-email-puck.chen@hisilicon.com> References: <1441865490-104686-1-git-send-email-puck.chen@hisilicon.com> <1441865490-104686-3-git-send-email-puck.chen@hisilicon.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:96de:80ff:fec2:9969 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Donnerstag, den 10.09.2015, 14:11 +0800 schrieb Chen Feng: > Add reset driver for hi6220-hikey board,this driver supply deassert > of IP. on hi6220 SoC. > > Signed-off-by: Chen Feng > --- > drivers/reset/Kconfig | 1 + > drivers/reset/Makefile | 1 + > drivers/reset/hisilicon/Kconfig | 5 +++ > drivers/reset/hisilicon/Makefile | 1 + > drivers/reset/hisilicon/hi6220_reset.c | 74 ++++++++++++++++++++++++++++++++++ > 5 files changed, 82 insertions(+) > create mode 100644 drivers/reset/hisilicon/Kconfig > create mode 100644 drivers/reset/hisilicon/Makefile > create mode 100644 drivers/reset/hisilicon/hi6220_reset.c > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > index 0615f50..df37212 100644 > --- a/drivers/reset/Kconfig > +++ b/drivers/reset/Kconfig > @@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER > If unsure, say no. > > source "drivers/reset/sti/Kconfig" > +source "drivers/reset/hisilicon/Kconfig" > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 157d421..331d7b2 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o > obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o > obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o > obj-$(CONFIG_ARCH_STI) += sti/ > +obj-$(CONFIG_ARCH_HISI) += hisilicon/ > diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig > new file mode 100644 > index 0000000..bceed14 > --- /dev/null > +++ b/drivers/reset/hisilicon/Kconfig > @@ -0,0 +1,5 @@ > +config COMMON_RESET_HI6220 > + tristate "Hi6220 Clock Driver" "Clock"? Should probably be "Reset". > + depends on (ARCH_HISI && RESET_CONTROLLER) > + help > + Build the Hisilicon Hi6220 reset driver. > diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile > new file mode 100644 > index 0000000..c932f86 > --- /dev/null > +++ b/drivers/reset/hisilicon/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o > diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c > new file mode 100644 > index 0000000..a88fc57 > --- /dev/null > +++ b/drivers/reset/hisilicon/hi6220_reset.c > @@ -0,0 +1,74 @@ > +/* > + * Hisilicon Hi6220 reset controller driver > + * > + * Copyright (c) 2015 Hisilicon Limited. > + * > + * Author: Feng Chen > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static void __iomem *src_base; > +static DEFINE_SPINLOCK(reset_lock); > + > +static int hi6220_reset_module(struct reset_controller_dev *rc_dev, > + unsigned long idx) > +{ > + unsigned long timeout; > + unsigned long flags; > + int bit; > + u32 val; > + > + int bank = idx >> 8; > + int offset = idx & 0xff; > + > + spin_lock_irqsave(&reset_lock, flags); > + > + val = readl(src_base + (bank * 0x10)); > + writel(val | BIT(offset), src_base + (bank * 0x10)); Are these registers write-once, otherwise any reason not to implement reset_assert, too? > + spin_unlock_irqrestore(&reset_lock, flags); > + > + return 0; > + > +} > + > +static struct reset_control_ops hi6220_reset_ops = { > + .deassert = hi6220_reset_module, > +}; > + > +static struct reset_controller_dev hi6220_reset_dev = { > + .ops = &hi6220_reset_ops, > + .nr_resets = 0xffff, This can't be correct, you only have 4 KiB register space. > +}; > + > +static void __init hi6220_reset_init(void) > +{ > + struct device_node *np; > + struct reset_control *test = NULL; > + > + np = of_find_compatible_node(NULL, NULL, "hisilicon,hisi_reset_ctl"); Better use "hisilicon,hi6220-reset-ctl" instead. > + if (!np) { > + pr_err("find reset node in dts error!\n"); > + return; > + } > + src_base = of_iomap(np, 0); > + WARN_ON(!src_base); > + > + hi6220_reset_dev.of_node = np; > + if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) > + reset_controller_register(&hi6220_reset_dev); > +} > + > +postcore_initcall(hi6220_reset_init); > + Drop this empty line. best regards Philipp