From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753256AbbINGvq (ORCPT ); Mon, 14 Sep 2015 02:51:46 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:16816 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752028AbbINGvd (ORCPT ); Mon, 14 Sep 2015 02:51:33 -0400 From: Jisheng Zhang To: , CC: , , Jisheng Zhang Subject: [PATCH RESEND 1/2] arm: berlin: use non-self-cleared reset register to reset cpu Date: Mon, 14 Sep 2015 14:47:44 +0800 Message-ID: <1442213265-1002-2-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1442213265-1002-1-git-send-email-jszhang@marvell.com> References: <1442213265-1002-1-git-send-email-jszhang@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2015-09-14_01:,, signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 kscore.is_bulkscore=0 kscore.compositescore=1 compositescore=0.9 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 kscore.is_spamscore=0 rbsscore=0.9 spamscore=0 urlsuspectscore=0.9 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1509140127 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In Berlin SoCs, there are two kinds of cpu reset control registers: the first one's corresponding bits will be self-cleared after some cycles, while the second one's bits won't. Previously the first kind of reset control register is used, this patch uses the second kind one to prepare for the next hotplug commit. Signed-off-by: Jisheng Zhang --- arch/arm/mach-berlin/platsmp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c index 34a3753..bde327b 100644 --- a/arch/arm/mach-berlin/platsmp.c +++ b/arch/arm/mach-berlin/platsmp.c @@ -17,7 +17,7 @@ #include #include -#define CPU_RESET 0x00 +#define CPU_RESET 0x20 #define RESET_VECT 0x00 #define SW_RESET_ADDR 0x94 @@ -31,6 +31,8 @@ static inline void berlin_perform_reset_cpu(unsigned int cpu) u32 val; val = readl(cpu_ctrl + CPU_RESET); + val &= ~BIT(cpu_logical_map(cpu)); + writel(val, cpu_ctrl + CPU_RESET); val |= BIT(cpu_logical_map(cpu)); writel(val, cpu_ctrl + CPU_RESET); } -- 2.5.1