From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751358AbbIOEAr (ORCPT ); Tue, 15 Sep 2015 00:00:47 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:44354 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750698AbbIOEAp (ORCPT ); Tue, 15 Sep 2015 00:00:45 -0400 From: Chen Feng To: , , , , , , , , CC: , , , , , Subject: [PATCH V3 1/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Date: Tue, 15 Sep 2015 11:58:22 +0800 Message-ID: <1442289504-183550-1-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.141.105.115] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.55F7976D.0103,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d8e6c9a1ff31e6d7ffc49fdb044a89e7 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add reset controller for hi6220 hikey-board. Signed-off-by: Chen Feng --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 3f03380..3bbc846 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -167,5 +167,12 @@ clocks = <&ao_ctrl 36>, <&ao_ctrl 36>; clock-names = "uartclk", "apb_pclk"; }; + + reset_ctrl: reset_ctrl@f7030000 { + compatible = "hisilicon,hi6220_reset_ctl"; + reg = <0x0 0xf7030000 0x0 0x1000>; + #reset-cells = <1>; + }; + }; }; -- 1.9.1