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From: Barry Song <21cnbao@gmail.com>
To: broonie@kernel.org, gregkh@linuxfoundation.org,
	sameo@linux.intel.com, lee.jones@linaro.org
Cc: linux-kernel@vger.kernel.org, workgroup.linux@csr.com,
	Guo Zeng <Guo.Zeng@csr.com>, Barry Song <Baohua.Song@csr.com>
Subject: [PATCH v2 1/3] regmap: irq: add support for chips who have separate unmask registers
Date: Thu, 17 Sep 2015 05:23:20 +0000	[thread overview]
Message-ID: <1442467402-7605-1-git-send-email-21cnbao@gmail.com> (raw)

From: Guo Zeng <Guo.Zeng@csr.com>

Some chips have separate unmask registers from mask registers for
some consideration of concurrency SMP write performance. And this
patch adds a flag for it.

An user will be CSR SiRFSoC ARM chips.

Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
 drivers/base/regmap/regmap-irq.c | 28 ++++++++++++++++++++++++++--
 include/linux/regmap.h           |  3 +++
 2 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
index 38d1f72..1821c3b 100644
--- a/drivers/base/regmap/regmap-irq.c
+++ b/drivers/base/regmap/regmap-irq.c
@@ -63,6 +63,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
 	struct regmap *map = d->map;
 	int i, ret;
 	u32 reg;
+	u32 unmask_offset;
 
 	if (d->chip->runtime_pm) {
 		ret = pm_runtime_get_sync(map->dev);
@@ -82,7 +83,22 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
 		if (d->chip->mask_invert)
 			ret = regmap_update_bits(d->map, reg,
 					 d->mask_buf_def[i], ~d->mask_buf[i]);
-		else
+		else if (d->chip->unmask_base) {
+			/* set mask with mask_base register */
+			ret = regmap_update_bits(d->map, reg,
+					d->mask_buf_def[i], ~d->mask_buf[i]);
+			if (ret < 0)
+				dev_err(d->map->dev,
+					"Failed to sync unmasks in %x\n",
+					reg);
+			unmask_offset = d->chip->unmask_base -
+							d->chip->mask_base;
+			/* clear mask with unmask_base register */
+			ret = regmap_update_bits(d->map,
+					reg + unmask_offset,
+					d->mask_buf_def[i],
+					d->mask_buf[i]);
+		} else
 			ret = regmap_update_bits(d->map, reg,
 					 d->mask_buf_def[i], d->mask_buf[i]);
 		if (ret != 0)
@@ -339,6 +355,7 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 	int i;
 	int ret = -ENOMEM;
 	u32 reg;
+	u32 unmask_offset;
 
 	if (chip->num_regs <= 0)
 		return -EINVAL;
@@ -420,7 +437,14 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 		if (chip->mask_invert)
 			ret = regmap_update_bits(map, reg,
 					 d->mask_buf[i], ~d->mask_buf[i]);
-		else
+		else if (d->chip->unmask_base) {
+			unmask_offset = d->chip->unmask_base -
+					d->chip->mask_base;
+			ret = regmap_update_bits(d->map,
+					reg + unmask_offset,
+					d->mask_buf[i],
+					d->mask_buf[i]);
+		} else
 			ret = regmap_update_bits(map, reg,
 					 d->mask_buf[i], d->mask_buf[i]);
 		if (ret != 0) {
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 8fc0bfd..f98fe9f 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -800,6 +800,8 @@ struct regmap_irq {
  *
  * @status_base: Base status register address.
  * @mask_base:   Base mask register address.
+ * @unmask_base:  Base unmask register address. for chips who have
+ *                separate mask and unmask registers
  * @ack_base:    Base ack address. If zero then the chip is clear on read.
  *               Using zero value is possible with @use_ack bit.
  * @wake_base:   Base address for wake enables.  If zero unsupported.
@@ -820,6 +822,7 @@ struct regmap_irq_chip {
 
 	unsigned int status_base;
 	unsigned int mask_base;
+	unsigned int unmask_base;
 	unsigned int ack_base;
 	unsigned int wake_base;
 	unsigned int irq_reg_stride;
-- 
1.9.1


             reply	other threads:[~2015-09-17  5:15 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-17  5:23 Barry Song [this message]
2015-09-17  5:23 ` [PATCH v2 2/3] regmap: irq: add ack_invert flag for chips using cleared bits as ack Barry Song
2015-09-17  5:23 ` [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management module driver Barry Song
2015-09-20  4:15   ` Lee Jones
2015-09-21  2:38     ` Barry Song
2015-09-24 18:13       ` Lee Jones
2015-09-29  6:18         ` Barry Song
2015-09-29  7:16           ` Lee Jones
2015-09-29  8:30             ` Barry Song
2015-09-29  8:55               ` Lee Jones
2015-10-04 10:02                 ` Barry Song
2015-10-05  8:21                   ` Lee Jones
2015-10-05 10:08                     ` Barry Song
2015-10-05 10:22                       ` Lee Jones
2015-09-17 10:53 ` [PATCH v2 1/3] regmap: irq: add support for chips who have separate unmask registers Mark Brown
2015-09-17 14:20   ` Barry Song

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