From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754029AbbIQHwP (ORCPT ); Thu, 17 Sep 2015 03:52:15 -0400 Received: from mail-pa0-f44.google.com ([209.85.220.44]:34261 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753367AbbIQHwN (ORCPT ); Thu, 17 Sep 2015 03:52:13 -0400 From: Caesar Wang To: Heiko Stuebner , Daniel Lezcano , Catalin Marinas , Will Deacon Cc: Caesar Wang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Gleixner , Kumar Gala , Ian Campbell , linux-rockchip@lists.infradead.org, Rob Herring , Pawel Moll , Olof Johansson , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/3] Support the timer on RK3368 SoC Date: Thu, 17 Sep 2015 15:51:09 +0800 Message-Id: <1442476272-31723-1-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Timer0~11 count up from zero to a programmed value and generate an interrupt when the count reaches the programmed value. TIMER0, TIMER1, TIMER2, Timer3, TIMER4 and TIMER5 are in the CPU subsystem, using timer ch0 ~ ch5 respectively. The timer clock is 24MHz OSC. This series are found on RK3368 SoC, verified on rk3368 evb board. Caesar Wang (3): clocksource: rockchip: Make the driver more readability and compatible arm64: Enable the timer on Rockchip architecture arm64: dts: rockchip: Add the needed timer for rk3368 SoC arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/rockchip/rk3368.dtsi | 6 ++++++ drivers/clocksource/rockchip_timer.c | 29 +++++++++++++++-------------- 3 files changed, 22 insertions(+), 14 deletions(-) -- 1.9.1