From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752345AbbIQRhx (ORCPT ); Thu, 17 Sep 2015 13:37:53 -0400 Received: from mout.gmx.net ([212.227.17.20]:54400 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752261AbbIQRhv (ORCPT ); Thu, 17 Sep 2015 13:37:51 -0400 From: Oleksij Rempel To: linux-kernel@vger.kernel.org, marc.zyngier@arm.com, jason@lakedaemon.net, tglx@linutronix.de Cc: Oleksij Rempel Subject: [PATCH 1/2] ARM: irqchip: mxs: prepare driver for HW with different offsets Date: Thu, 17 Sep 2015 19:37:28 +0200 Message-Id: <1442511449-7639-1-git-send-email-linux@rempel-privat.de> X-Mailer: git-send-email 2.5.0 X-Provags-ID: V03:K0:YSsKL9Gv1zZFAvGs3udY/NhlAhJyw9P4FIacMK75MGiKrYnUjy7 GTk6iec0Nt9ZX70AxurlMfKdVW1zi78hw+Wy6ESMmVhRR1LgdSR3/OEZm23THkWdvv3ViuQ U5zjUtkKaRZjfEjlegd5ZnqTjur7uyOr7wYVC2eVFCCleWvvf1+5Q9EHAr+Yw09KX9Kx9KU 2HWg1e2bMtnur72pVdhRw== X-UI-Out-Filterresults: notjunk:1;V01:K0:S1NAR75fnKo=:EvC+Ts6g22k44DcTlFN2EJ jwFgtZecwA8RkVLwAbUXBEW9tDNw/Fyz///oBXFiyg/T0/cLd3bFu1tFC0MFNM7198ewL5Hqw nTmawlr/NMZKN8YNRmiB3OaN4SI3hHNuONsO6q9gzP7oKmspRT8BfzNaou2vIKuI82hXI/mzo 3N6yqyui7r/hVk9MPBggY7WeneSbGQyEBwgPO3aQ1G3tuqDssF1pBTSGcp65BgFEXOBrDnOpL 1C+ty0nyzOIo1iPoF4dIpCb40+hHsKL4ySin+a+ymd7K0ml5HsINtEyvmfPfkybVHSnzKM8k/ DCuvU/4/Dik0vASF9DT+deHmA0NtFu81i+kmyJ0YiySIYqiOb8R5BOuo9H+bOPGctziKNSX8i L+Bm0c7b3hdgzWVrGMyFQmBx9L7MYUbZVzh7An2hfr7cb21hNwxPTQKVxrUcpSFXWl3H2hAbg RH43DcGhwKLLl2xpOjDQHLbMmpLpv6RkSAa1nqut6BJ4mfTJNltndq+Uf6X/NW2hvo7W4XqEb 4fVYy5y5IcWaG8Up5ZrIRsr7SvPKyQIOugB7HhO7yZDFg5mfnP9HoSX83dKozEzRiFCMcyjdw DooZxem+fFd74REiynjJLpx/qFVSlsY+iRGfhOLizm3AQoH6HRC9z+zWVbuPamtI/pNMPP6Zn qVXwIK/Eo6OKO7aQXrIjg9/eQbBoxAxoWvLPgbMaJlR1zxhTBU2Tk2x7vDVs4A4ZGtkNf0jNf qtLV0It4PdQsSANF Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some HW has similar functionality but different register offsets. Make sure we can change offsets dynamically. Signed-off-by: Oleksij Rempel --- drivers/irqchip/irq-mxs.c | 55 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 42 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-mxs.c b/drivers/irqchip/irq-mxs.c index 1faf812..c8d2ac1 100644 --- a/drivers/irqchip/irq-mxs.c +++ b/drivers/irqchip/irq-mxs.c @@ -28,18 +28,39 @@ #include #include +/* + * this device provide 4 offsets for each register: + * 0x0 - plain read write mode + * 0x4 - set mode, OR logic. + * 0x8 - clr mode, XOR logic. + * 0xc - togle mode. + */ +#define SET_REG 4 +#define CLR_REG 8 + #define HW_ICOLL_VECTOR 0x0000 #define HW_ICOLL_LEVELACK 0x0010 #define HW_ICOLL_CTRL 0x0020 #define HW_ICOLL_STAT_OFFSET 0x0070 -#define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10) -#define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10) -#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 +#define HW_ICOLL_INTERRUPT0 0x0120 +#define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10) +#define BM_ICOLL_INTR_ENABLE BIT(2) #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 #define ICOLL_NUM_IRQS 128 -static void __iomem *icoll_base; +struct icoll_priv { + void __iomem *vector; + void __iomem *levelack; + void __iomem *ctrl; + void __iomem *stat; + void __iomem *intr; + /* number of interrupts per register */ + int intr_per_reg; + void __iomem *clear; +}; + +static struct icoll_priv icoll_priv; static struct irq_domain *icoll_domain; static void icoll_ack_irq(struct irq_data *d) @@ -50,19 +71,19 @@ static void icoll_ack_irq(struct irq_data *d) * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally. */ __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, - icoll_base + HW_ICOLL_LEVELACK); + icoll_priv.levelack); } static void icoll_mask_irq(struct irq_data *d) { - __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, - icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq)); + __raw_writel(BM_ICOLL_INTR_ENABLE, + icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); } static void icoll_unmask_irq(struct irq_data *d) { - __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, - icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq)); + __raw_writel(BM_ICOLL_INTR_ENABLE, + icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); } static struct irq_chip mxs_icoll_chip = { @@ -75,8 +96,8 @@ asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) { u32 irqnr; - irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET); - __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR); + irqnr = __raw_readl(icoll_priv.stat); + __raw_writel(irqnr, icoll_priv.vector); handle_domain_irq(icoll_domain, irqnr, regs); } @@ -97,14 +118,22 @@ static const struct irq_domain_ops icoll_irq_domain_ops = { static int __init icoll_of_init(struct device_node *np, struct device_node *interrupt_parent) { - icoll_base = of_iomap(np, 0); + void __iomem *icoll_base = of_iomap(np, 0); WARN_ON(!icoll_base); + icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR; + icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK; + icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL; + icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET; + icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0; + icoll_priv.intr_per_reg = 1; + icoll_priv.clear = NULL; + /* * Interrupt Collector reset, which initializes the priority * for each irq to level 0. */ - stmp_reset_block(icoll_base + HW_ICOLL_CTRL); + stmp_reset_block(icoll_priv.ctrl); icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS, &icoll_irq_domain_ops, NULL); -- 2.5.0