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Peter Anvin" CC: Daniel J Blueman , , , Daniel Lezcano Subject: [PATCH v2] x86: Introduce Numachip2 timer mechanisms Date: Mon, 21 Sep 2015 18:02:25 +0800 Message-ID: <1442829745-29311-1-git-send-email-daniel@numascale.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1442768522-19217-4-git-send-email-daniel@numascale.com> References: <1442768522-19217-4-git-send-email-daniel@numascale.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [115.42.131.38] X-ClientProxiedBy: DB3PR05CA0051.eurprd05.prod.outlook.com (25.160.41.179) To AM4PR07MB1299.eurprd07.prod.outlook.com (25.164.81.157) X-Microsoft-Exchange-Diagnostics: 1;AM4PR07MB1299;2:JMpA4CWbKI/SeBs5hMP6CQk+5zRbfRwCzOeYdIys9OHL3YC7eGKHO8qC3WAgJY+RNFEkOGk0uNiCG7rkwzjWuBKa81e0dg7nub2edVIlZ2rRXWgq429dYs3VJdEFAjPIAC0aEQ1NMKItWOS+Vf93I3PB0hu0cVdRfIHlVnSIby8=;3:pA3JsRESo8t1pU0OfOqQWonp3SOZxsDgDAuZA8ZXsKZ21vCQNVFOPi8ofMBv/NrBLH01CO1aR7na62ob8y9IAGOnFAmF95MS/fA1YBKN3wDc5W7n+RyM+kXz4eBZhWaWo5CtCyr0vV9qL/y0lY14sg==;25:FMsgIMK+LbriQdzZLFPUpzO98Lyv7x708u+ozt3Z5d/p2S41OEuPgKSNYglR/jMdYzQg7BJDFZ/O9Tcs18B/RO0hXu0gXZ0ONquRLHjABjig08iY22YDw6w4c8t8veSmGYrxkCaQ6p9UCfsfo2lDPpvMcx8lD0AbY2bGFdxLZld+v4Dz23ae3ItBt02n60q8Uqo8rJkxoCAkCBQ4hmOHi4lRsBhYPhlGkH2cjwxJoYGM9iUXRtdPWEdpXah15VpX;4:SW2oaVshjcpo3GolVpFzeelT4neHmc5Cqef2rDTLtMSfCVPiI+otLj3yH82APH4hgUuKev4ow9DC5i0AoQsW2Y1zolSmZe9j76YyEeAUBM1twHlH1Zz2uzadEPnyH/o4o2sm+wEsHbj8boZCUsKZ4ElJwYCHWQOAfR4gRvYHG6Ye79JzEe+X5/xbtjPGqKueAP0n28dmgagr1PpsDRRfcau8aEKb/7Zm96JzdmqHsWk= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1299; X-Exchange-Antispam-Report-CFA: BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1299;BCL:0;PCL:0;RULEID:;SRVR:AM4PR07MB1299; X-Forefront-PRVS: 07063A0A30 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10019020)(6009001)(189002)(199003)(5003940100001)(19580395003)(87976001)(50226001)(86362001)(122386002)(76176999)(189998001)(33646002)(50986999)(5004730100002)(19580405001)(101416001)(62966003)(40100003)(42186005)(68736005)(81156007)(4001540100001)(92566002)(50466002)(77096005)(36756003)(46102003)(97736004)(2950100001)(5001860100001)(66066001)(229853001)(48376002)(5001830100001)(106356001)(5001770100001)(47776003)(64706001)(105586002)(77156002)(2004002);DIR:OUT;SFP:1102;SCL:1;SRVR:AM4PR07MB1299;H:meiko.int.numascale.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;AM4PR07MB1299;23:OCb18ebklBLvD+a0jOiHRo/+agYJHxDWLOQLh0yQb?= =?us-ascii?Q?atkHz/QjW52CpjWR2qcsMAq6Zc9gk3Dh1Lx3iKZmFD2KKz5L18s1Mb70Vpj1?= =?us-ascii?Q?Kc+HJH+mC8aHd60ZMkH+5w3H3nKQPiMqA2DBXekIfamYXm3ql+al5IZ22evS?= =?us-ascii?Q?mMPo64w5gImiZMCTVzBuhsG5dDzGhcAW8jY44Yod/YSyQEeLOr3uXXyEnpzI?= =?us-ascii?Q?65xW2POgl/db0JzEBZKI674g/vxDZ2WM6Ls6iwuDZe21wA5hRsahB/QR1mEe?= =?us-ascii?Q?lkXx5IMn1MnAQsko/n1Glp6hsHrokf6I1fLsEMP7j71aYXevsasD9M289F3Z?= =?us-ascii?Q?WMFROSm6ncBYY4jgzDfMjeuAOadB/HhJP04N7TwISgEcGsxFlPaQhwiFfYAn?= =?us-ascii?Q?87ARcmc/N4ohBN1AM8CVgH3KtM5/RJO7acy2LNqZvMq7PerO6qOjAqoQGLPQ?= =?us-ascii?Q?UH/lJ8TCXEeG0M8zTylqPz/2GD4LHlioHpCbQSunF/9vtHYppRjakkxYUicA?= =?us-ascii?Q?1WIqdSk7ztHD2gKoyHKLJCLbMJJIMy3ddGONLHQNVOC1I0Ld/VqdUq1wnf/w?= =?us-ascii?Q?XtfdlkGxzo+UMBfhgUZB1F74HkgY7u/6wy+Gn39/NVRYjRR/aTh8wjl3PtyJ?= =?us-ascii?Q?vFw2VPl89t80IZvU/hp8OyH6zB72m9DdBUidfE5Yq/hRlRG4ubXsM8BdDmmR?= =?us-ascii?Q?XrppokFSobig0JTjEykRCojq5UxmQKdIpaFrt8kgZK5negpQzFUcikVIOZsE?= =?us-ascii?Q?VnnLRkf1qGDqGDBYtF2Va0RdtqcqNNbHWJ0qo9sfchCm6JqoJvpHuuaZ1no2?= =?us-ascii?Q?BiiFi4xYg7nl8VG67/AGvL8nfsf34yBIGV4lcThdaPIwHhQo4b1qJ7cJhYZW?= =?us-ascii?Q?bxgKTWfh/SaejyY1WxjQJysm00a/qkN9+iLvzTSF6Pz3vF3cB8MAkk4Bba8i?= =?us-ascii?Q?qQLSPY2hkyvWMLKlIfxoQpvj7uQectzxo4K1WGhyWayyNhR4A2FJgwf6mvQA?= =?us-ascii?Q?BmeAfCy/lg00a5Opar5f4ALw1BtrTGNMSkVEy8xbtLVxM+yKauhUhBExqu8d?= =?us-ascii?Q?uvivzKikI+kdcveRNAaEp4LiD8K6k8ukfZFlBOCUIK9Gum8Xtd4ZzZoj5WOx?= =?us-ascii?Q?QQyLXEeGLk=3D?= X-Microsoft-Exchange-Diagnostics: 1;AM4PR07MB1299;5:/WvNTuW/Zlma6mRu9IFkeK3WQR8dsagMxxYyhHiFhpjhqoHIftTWKbS/BXLoPMxRWQTxilhtKP0yTwjfjnS9kQrkJBiF2eoZsWrDFgarpkrlVQApdHWfHwypII/xb6sZn/ceMBiAeWnh5SN8iAqB0w==;24:Gc11CZW4immkdcWNn1bTJ23HA9BDAuQQ7Qq1sKQq+rPls/IpGeC0ao4AqI4ScWVGXyhYtcx3p+s0qe43FDP69WKJKGicgfd5R102UDbRxv0=;20:VduQFH+LfYZTQ+rjuuyeyjVvUk2luExhR476PbWoFaCSmqVhF1OrhYIPSB4V/4rJ1fmvGaGYjYRFJtHJGTg65Q== SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: numascale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Sep 2015 10:03:04.2757 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR07MB1299 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add 1GHz 64-bit Numachip2 clocksource timer support for accurate system-wide timekeeping, as core TSCs are unsynchronised. Additionally, add a per-core clockevent mechanism that interrupts via the platform IPI vector after a programmed period. v2: Fix whitespace and wrapping issue Signed-off-by: Daniel J Blueman Acked-by: Steffen Persvold --- arch/x86/include/asm/numachip/numachip_csr.h | 9 +++ drivers/clocksource/Makefile | 1 + drivers/clocksource/numachip.c | 95 ++++++++++++++++++++++++++++ 3 files changed, 105 insertions(+) create mode 100644 drivers/clocksource/numachip.c diff --git a/arch/x86/include/asm/numachip/numachip_csr.h b/arch/x86/include/asm/numachip/numachip_csr.h index e09d845..29719ee 100644 --- a/arch/x86/include/asm/numachip/numachip_csr.h +++ b/arch/x86/include/asm/numachip/numachip_csr.h @@ -59,6 +59,10 @@ static inline void write_lcsr(unsigned long offset, unsigned int val) #define NUMACHIP2_LCSR_BASE 0xf0000000UL #define NUMACHIP2_LCSR_SIZE 0x1000000UL #define NUMACHIP2_APIC_ICR 0x100000 +#define NUMACHIP2_TIMER_DEADLINE 0x200000 +#define NUMACHIP2_TIMER_INT 0x200008 +#define NUMACHIP2_TIMER_NOW 0x200018 +#define NUMACHIP2_TIMER_RESET 0x200020 static inline void __iomem *numachip2_lcsr_address(unsigned long offset) { @@ -86,4 +90,9 @@ static inline void numachip2_write64_lcsr(unsigned long offset, u64 val) writeq(val, numachip2_lcsr_address(offset)); } +static inline unsigned int numachip2_timer(void) +{ + return (smp_processor_id() % 48) << 6; +} + #endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */ diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 5c00863..57dfad3 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -62,3 +62,4 @@ obj-$(CONFIG_H8300) += h8300_timer8.o obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o +obj-$(CONFIG_X86_NUMACHIP) += numachip.o diff --git a/drivers/clocksource/numachip.c b/drivers/clocksource/numachip.c new file mode 100644 index 0000000..088e5fa --- /dev/null +++ b/drivers/clocksource/numachip.c @@ -0,0 +1,95 @@ +/* + * + * Copyright (C) 2015 Numascale AS. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +#include +#include +#include + +static DEFINE_PER_CPU(struct clock_event_device, cpu_ced); + +static cycles_t numachip2_timer_read(struct clocksource *cs) +{ + return numachip2_read64_lcsr(NUMACHIP2_TIMER_NOW); +} + +static struct clocksource numachip2_clocksource = { + .name = "numachip2", + .rating = 295, + .read = numachip2_timer_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .mult = 1, + .shift = 0, +}; + +static int numachip2_set_next_event(unsigned long delta, struct clock_event_device *ced) +{ + numachip2_write64_lcsr(NUMACHIP2_TIMER_DEADLINE + numachip2_timer(), + delta); + return 0; +} + +static struct clock_event_device numachip2_clockevent = { + .name = "numachip2", + .rating = 400, + .set_next_event = numachip2_set_next_event, + .features = CLOCK_EVT_FEAT_ONESHOT, + .mult = 1, + .shift = 0, + .min_delta_ns = 1250, + .max_delta_ns = LONG_MAX, +}; + +static void numachip_timer_interrupt(void) +{ + struct clock_event_device *ced = this_cpu_ptr(&cpu_ced); + + ced->event_handler(ced); +} + +static __init void numachip_timer_each(struct work_struct *work) +{ + unsigned local_apicid = __this_cpu_read(x86_cpu_to_apicid) & 0xff; + struct clock_event_device *ced = this_cpu_ptr(&cpu_ced); + + /* Setup IPI vector to local core and relative timing mode */ + numachip2_write64_lcsr(NUMACHIP2_TIMER_INT + numachip2_timer(), + (3 << 22) | (X86_PLATFORM_IPI_VECTOR << 14) | + (local_apicid << 6)); + + *ced = numachip2_clockevent; + ced->cpumask = cpumask_of(smp_processor_id()); + clockevents_register_device(ced); +} + +static int __init numachip_timer_init(void) +{ + if (numachip_system != 2) + return -ENODEV; + + /* Reset timer */ + numachip2_write64_lcsr(NUMACHIP2_TIMER_RESET, 0); + clocksource_register_hz(&numachip2_clocksource, NSEC_PER_SEC); + + /* Setup per-cpu clockevents */ + x86_platform_ipi_callback = numachip_timer_interrupt; + schedule_on_each_cpu(&numachip_timer_each); + + return 0; +} + +arch_initcall(numachip_timer_init); -- 2.5.0