[PATCH V2 1/3] EDAC, amd64_edac: Extend scrub rate programmability feature for F15hM60h

[Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>]

For F15h M60h processor, the scrub rate control register has moved
to F2 of PCI config space and is at a different offset from
earlier processors. The minimun recommended scrub rate is also different.
(Refer D18F2x1c9_dct[1:0][DramScrub] on Fam15hM60h BKDG)

Modify the set_scrub_rate() and get_scrub_rate() functions so that
they are aware of these changes.

Tested on F15hM60h, Fam15h Models 00h-0fh and Fam10h systems and
it works fine.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
 drivers/edac/amd64_edac.c | 23 +++++++++++++++++++----
 drivers/edac/amd64_edac.h |  2 ++
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 73aea40..0ae72b9 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -173,7 +173,7 @@ static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
  * scan the scrub rate mapping table for a close or matching bandwidth value to
  * issue. If requested is too big, then use last maximum value found.
  */
-static int __set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
+static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
 {
 	u32 scrubval;
 	int i;
@@ -201,7 +201,14 @@ static int __set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
 
 	scrubval = scrubrates[i].scrubval;
 
-	pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F);
+	if (pvt->fam == 0x15 && pvt->model == 0x60) {
+		f15h_select_dct(pvt, 0);
+		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
+		f15h_select_dct(pvt, 1);
+		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
+	} else {
+		pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);
+	}
 
 	if (scrubval)
 		return scrubrates[i].bandwidth;
@@ -216,12 +223,17 @@ static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
 
 	if (pvt->fam == 0xf)
 		min_scrubrate = 0x0;
+	else if (pvt->fam == 0x15 && pvt->model == 0x60)
+		min_scrubrate = 0x6;
 
 	/* Erratum #505 */
 	if (pvt->fam == 0x15 && pvt->model < 0x10)
 		f15h_select_dct(pvt, 0);
 
-	return __set_scrub_rate(pvt->F3, bw, min_scrubrate);
+	if (pvt->fam == 0x15 && pvt->model == 0x60)
+		return __set_scrub_rate(pvt, bw, min_scrubrate);
+
+	return __set_scrub_rate(pvt, bw, min_scrubrate);
 }
 
 static int get_scrub_rate(struct mem_ctl_info *mci)
@@ -234,7 +246,10 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
 	if (pvt->fam == 0x15 && pvt->model < 0x10)
 		f15h_select_dct(pvt, 0);
 
-	amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
+	if (pvt->fam == 0x15 && pvt->model == 0x60)
+		amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
+	else
+		amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
 
 	scrubval = scrubval & 0x001F;
 
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 4bdec75..971dc12 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -255,6 +255,8 @@
 
 #define DCT_SEL_HI			0x114
 
+#define F15H_M60H_SCRCTRL		0x1C8
+
 /*
  * Function 3 - Misc Control
  */
-- 
2.4.0