From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751892AbbJBGwd (ORCPT ); Fri, 2 Oct 2015 02:52:33 -0400 Received: from mga09.intel.com ([134.134.136.24]:49949 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751695AbbJBGwa (ORCPT ); Fri, 2 Oct 2015 02:52:30 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,622,1437462000"; d="scan'208";a="656393906" From: Fenghua Yu To: "H Peter Anvin" , "Ingo Molnar" , "Thomas Gleixner" , "Peter Zijlstra" Cc: "linux-kernel" , "x86" , "Fenghua Yu" , "Vikas Shivappa" Subject: [PATCH V2 1/5] x86/intel_rdt: Intel Code Data Prioritization detection Date: Thu, 1 Oct 2015 23:33:55 -0700 Message-Id: <1443767639-62457-2-git-send-email-fenghua.yu@intel.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1443767639-62457-1-git-send-email-fenghua.yu@intel.com> References: <1443767639-62457-1-git-send-email-fenghua.yu@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds enumeration support for Code Data Prioritization(CDP) feature found in future Intel Xeon processors. It includes CPUID enumeration routines for CDP. CDP is an extension to Cache Allocation and lets threads allocate subset of L3 cache for code and data separately. The allocation is represented by the code or data cache capacity bit mask(cbm) MSRs IA32_L3_QOS_MASK_n. Each Class of service would be associated with one dcache_cbm and one icache_cbm MSR and hence the number of available CLOSids is halved with CDP. The association for a CLOSid 'n' is shown below : data_cbm_address (n) = base + (n <<1) code_cbm_address (n) = base + (n <<1) +1. During scheduling the kernel writes the CLOSid of the thread to IA32_PQR_ASSOC_MSR. Signed-off-by: Vikas Shivappa Signed-off-by: Fenghua Yu --- arch/x86/include/asm/cpufeature.h | 5 ++++- arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/cpu/intel_rdt.c | 2 ++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 4e93006..6dc0701 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -12,7 +12,7 @@ #include #endif -#define NCAPINTS 14 /* N 32-bit words worth of info */ +#define NCAPINTS 15 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* @@ -259,6 +259,9 @@ /* Intel-defined CPU features, CPUID level 0x00000010:0 (ebx), word 13 */ #define X86_FEATURE_CAT_L3 (13*32 + 1) /* Cache Allocation L3 */ +/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x00000010:1 (ecx), word 14 */ +#define X86_FEATURE_CDP_L3 (14*32 + 2) /* Code data prioritization L3 */ + /* * BUG word(s) */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 026a416..9886e23 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -666,6 +666,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) cpuid_count(0x00000010, 1, &eax, &ebx, &ecx, &edx); c->x86_cache_max_closid = edx + 1; c->x86_cache_max_cbm_len = eax + 1; + c->x86_capability[14] = ecx; } } diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c index cb4d2ef..29c8a19 100644 --- a/arch/x86/kernel/cpu/intel_rdt.c +++ b/arch/x86/kernel/cpu/intel_rdt.c @@ -561,6 +561,8 @@ static int __init intel_rdt_late_init(void) static_key_slow_inc(&rdt_enable_key); pr_info("Intel cache allocation enabled\n"); + if (cpu_has(c, X86_FEATURE_CDP_L3)) + pr_info("Intel code data prioritization detected\n"); out_err: return err; -- 1.8.1.2