From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753589AbbJBRzH (ORCPT ); Fri, 2 Oct 2015 13:55:07 -0400 Received: from mail-gw1-out.broadcom.com ([216.31.210.62]:53046 "EHLO mail-gw1-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753435AbbJBRzD (ORCPT ); Fri, 2 Oct 2015 13:55:03 -0400 X-IronPort-AV: E=Sophos;i="5.17,624,1437462000"; d="scan'208";a="76710001" From: Anup Patel To: CC: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , Kumar Gala , "Catalin Marinas" , Will Deacon , Ray Jui , Scott Branden , Florian Fainelli , Vikram Prakash , Anup Patel , Pramod KUMAR , , , Subject: [PATCH 3/6] arm64: dts: Add syscon based reboot in DT for NS2 Date: Fri, 2 Oct 2015 23:24:20 +0530 Message-ID: <1443808463-21120-4-git-send-email-anup.patel@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1443808463-21120-1-git-send-email-anup.patel@broadcom.com> References: <1443808463-21120-1-git-send-email-anup.patel@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To reset NS2, we simply have to write '0' to BIT[1] at offset 0x90 of CRMU space. The above can be easily achieved by writing 0xfffffffd at offset 0x90 using syscon-reboot driver. We don't need to have separate driver for rebooting NS2. This patch enables syscon-reboot driver for NS2 using DT. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index c5d90e4..5d2ac6b 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -144,6 +144,18 @@ mmu-masters; }; + crmu: crmu@65024000 { + compatible = "syscon"; + reg = <0x65024000 0x100>; + }; + + reboot@65024000 { + compatible ="syscon-reboot"; + regmap = <&crmu>; + offset = <0x90>; + mask = <0xfffffffd>; + }; + gic: interrupt-controller@65210000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- 1.9.1