From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752277AbbJEIHo (ORCPT ); Mon, 5 Oct 2015 04:07:44 -0400 Received: from mail-wi0-f170.google.com ([209.85.212.170]:36827 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751462AbbJEIHk (ORCPT ); Mon, 5 Oct 2015 04:07:40 -0400 From: Gabriel Fernandez To: Maxime Coquelin , Michael Turquette , Stephen Boyd , Gabriel Fernandez Cc: Peter Griffin , Pankaj Dev , Olivier Bideau , Geert Uytterhoeven , Fabian Frederick , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, linux-clk@vger.kernel.org Subject: [PATCH v3 0/4] ST PLL improvement Date: Mon, 5 Oct 2015 10:06:29 +0200 Message-Id: <1444032393-13433-1-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes in v3: - reorganize patch 1 and 2 to avoid a break git bisect Changes in v2: - Add const for st_pll4600c28_418_a9 structure - Use readl_relaxed_poll_timeout macro instead Jiffies - Add patch to enable stih418 A9 pll via DT. This patchset is based on '[PATCH 0/2] ST PLL fixes for 4.3' Gabriel Fernandez (4): drivers: clk: st: Support for enable/disable in Clockgen PLLs drivers: clk: st: PLL rate change implementation for DVFS drivers: clk: st: Correct the pll-type for A9 for stih418 ARM: STi: DT: Add support for stih418 A9 pll .../devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 + arch/arm/boot/dts/stih418-clock.dtsi | 2 +- drivers/clk/st/clkgen-mux.c | 3 + drivers/clk/st/clkgen-pll.c | 468 ++++++++++++++++++++- drivers/clk/st/clkgen.h | 2 + 5 files changed, 467 insertions(+), 9 deletions(-) -- 1.9.1