From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752889AbbJFO14 (ORCPT ); Tue, 6 Oct 2015 10:27:56 -0400 Received: from mail-wi0-f172.google.com ([209.85.212.172]:38508 "EHLO mail-wi0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752829AbbJFO1w (ORCPT ); Tue, 6 Oct 2015 10:27:52 -0400 From: Marc Titinger X-Google-Original-From: Marc Titinger To: khilman@kernel.org, rjw@rjwysocki.net Cc: lina.iyer@linaro.org, ahaslam@baylibre.com, bcousson@baylibre.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Titinger Subject: [RFC v2 1/6] arm64: Juno: declare generic power domains for both clusters. Date: Tue, 6 Oct 2015 16:27:40 +0200 Message-Id: <1444141665-18534-2-git-send-email-mtitinger+renesas@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444141665-18534-1-git-send-email-mtitinger+renesas@baylibre.com> References: <20151006022702.GA78570@linaro.org> <1444141665-18534-1-git-send-email-mtitinger+renesas@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-off-by: Marc Titinger --- arch/arm64/boot/dts/arm/juno.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index 342bb99..499f035 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -63,6 +63,7 @@ enable-method = "psci"; next-level-cache = <&A57_L2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + power-domains = <&a57_pd>; }; A57_1: cpu@1 { @@ -72,6 +73,7 @@ enable-method = "psci"; next-level-cache = <&A57_L2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + power-domains = <&a57_pd>; }; A53_0: cpu@100 { @@ -81,6 +83,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + power-domains = <&a53_pd>; }; A53_1: cpu@101 { @@ -90,6 +93,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + power-domains = <&a53_pd>; }; A53_2: cpu@102 { @@ -99,6 +103,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + power-domains = <&a53_pd>; }; A53_3: cpu@103 { @@ -108,6 +113,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + power-domains = <&a53_pd>; }; A57_L2: l2-cache0 { @@ -119,6 +125,19 @@ }; }; + pm-domains { + + a57_pd: a57_pd@ { + compatible = "arm,pd"; + #power-domain-cells = <0>; + }; + + a53_pd: a53_pd@ { + compatible = "arm,pd"; + #power-domain-cells = <0>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = , -- 1.9.1