From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964848AbbJHP4z (ORCPT ); Thu, 8 Oct 2015 11:56:55 -0400 Received: from mga03.intel.com ([134.134.136.65]:35144 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933809AbbJHP4y (ORCPT ); Thu, 8 Oct 2015 11:56:54 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,655,1437462000"; d="scan'208";a="576684582" From: Andy Shevchenko To: linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org Cc: Andy Shevchenko Subject: [PATCH 1/1] x86/cpu/intel: enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield Date: Thu, 8 Oct 2015 18:56:26 +0300 Message-Id: <1444319786-36125-1-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.5.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Intel Merrifield SoC is a successor of the Intel MID line of SoCs. Let's set the neccessary capability for that chip. See commit c54fdbb2823d (x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3) for the details. Signed-off-by: Andy Shevchenko --- arch/x86/kernel/cpu/intel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 98a13db..209ac1e 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) switch (c->x86_model) { case 0x27: /* Penwell */ case 0x35: /* Cloverview */ + case 0x4a: /* Merrifield */ set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); break; default: -- 2.5.3