From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754879AbbJHWp4 (ORCPT ); Thu, 8 Oct 2015 18:45:56 -0400 Received: from mail-oi0-f45.google.com ([209.85.218.45]:34981 "EHLO mail-oi0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751973AbbJHWpx (ORCPT ); Thu, 8 Oct 2015 18:45:53 -0400 From: Moritz Fischer To: michal.simek@xilinx.com Cc: soren.brinkmann@xilinx.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, dinguyen@opensource.altera.com, atull@opensource.altera.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, Moritz Fischer Subject: [PATCH 1/3] doc: dt: fpga: Added Documentation for Xilinx Zynq FPGA manager. Date: Fri, 9 Oct 2015 00:45:05 +0200 Message-Id: <1444344307-22509-2-git-send-email-moritz.fischer@ettus.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1444344307-22509-1-git-send-email-moritz.fischer@ettus.com> References: <1444344307-22509-1-git-send-email-moritz.fischer@ettus.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-off-by: Moritz Fischer --- .../bindings/fpga/xilinx-zynq-fpga-mgr.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt new file mode 100644 index 0000000..82ffda8 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt @@ -0,0 +1,26 @@ +Xilinx Zynq FPGA Manager + +Required properties: +- compatible: should contain "xlnx,zynq-devcfg-1.0" +- reg: base address and size for memory mapped io +- interrupt parent: interrupt source phandle +- interrupts: interrupt for the FPGA manager device +- clocks: phandle for clocks required operation +- syscon: phandle for access to SLCR registers + +Optional properties: +- clock-names: names for clocks + + + +Example: + devcfg: devcfg@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; + interrupt-parent = <&intc>; + interrupts = <0 8 4>; + clocks = <&clkc 12>; + clock-names = "ref_clk"; + syscon = <&slcr>; + }; + -- 2.6.1