From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934291AbbJIIoi (ORCPT ); Fri, 9 Oct 2015 04:44:38 -0400 Received: from down.free-electrons.com ([37.187.137.238]:52764 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934177AbbJIIof (ORCPT ); Fri, 9 Oct 2015 04:44:35 -0400 From: Maxime Ripard To: linux-arm-kernel@lists.infradead.org Cc: Chen-Yu Tsai , Hans de Goede , linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Maxime Ripard Subject: [PATCH v3 4/5] ARM: sun5i: dt: Add UART3 CTS and RTS pins Date: Fri, 9 Oct 2015 09:42:56 +0100 Message-Id: <1444380177-15302-5-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: <1444380177-15302-1-git-send-email-maxime.ripard@free-electrons.com> References: <1444380177-15302-1-git-send-email-maxime.ripard@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a separate pinctrl node for the UART3 CTS and RTS pins shared between the A10s and A13. Signed-off-by: Maxime Ripard Reviewed-by: Hans de Goede --- arch/arm/boot/dts/sun5i.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 433c83a321ca..7d355e52efe2 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -536,6 +536,13 @@ allwinner,drive = ; allwinner,pull = ; }; + + uart3_pins_cts_rts_a: uart3-cts-rts@0 { + allwinner,pins = "PG11", "PG12"; + allwinner,function = "uart3"; + allwinner,drive = ; + allwinner,pull = ; + }; }; timer@01c20c00 { -- 2.5.3