From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752089AbbJJJ46 (ORCPT ); Sat, 10 Oct 2015 05:56:58 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:33028 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751460AbbJJJ4y (ORCPT ); Sat, 10 Oct 2015 05:56:54 -0400 From: Chris Zhong To: heiko@sntech.de, linux-rockchip@lists.infradead.org Cc: Chris Zhong , Russell King , devicetree@vger.kernel.org, Kumar Gala , linux-kernel@vger.kernel.org, Ian Campbell , Rob Herring , Pawel Moll , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH 08/10] ARM: dts: rockchip: add rk3288 mipi_dsi nodes Date: Sat, 10 Oct 2015 17:55:28 +0800 Message-Id: <1444470930-17150-9-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1444470930-17150-1-git-send-email-zyw@rock-chips.com> References: <1444470930-17150-1-git-send-email-zyw@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl output port nodes. Signed-off-by: Chris Zhong --- arch/arm/boot/dts/rk3288.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 1a7cb08..3266d11 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -783,6 +783,10 @@ reg = <0>; remote-endpoint = <&hdmi_in_vopb>; }; + vopb_out_mipi: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_in_vopb>; + }; }; }; @@ -816,6 +820,10 @@ reg = <0>; remote-endpoint = <&hdmi_in_vopl>; }; + vopl_out_mipi: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_in_vopl>; + }; }; }; @@ -856,6 +864,37 @@ }; }; + mipi_dsi: mipi@ff960000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0xff960000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>; + clock-names = "ref", "pclk"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + }; + }; + gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; interrupt-controller; -- 2.6.1