From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751593AbbJLFu5 (ORCPT ); Mon, 12 Oct 2015 01:50:57 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:49592 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750890AbbJLFuu (ORCPT ); Mon, 12 Oct 2015 01:50:50 -0400 From: Jisheng Zhang To: , , , , , , , , CC: , , , , , Jisheng Zhang Subject: [PATCH 3/5] ARM: dts: berlin: add axi clock for BG2Q sdhci0 and sdhci1 Date: Mon, 12 Oct 2015 13:46:34 +0800 Message-ID: <1444628796-5484-4-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1444628796-5484-1-git-send-email-jszhang@marvell.com> References: <1444628796-5484-1-git-send-email-jszhang@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2015-10-12_03:,, signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1510120078 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the axi clock for BG2Q's sdhci0 and sdhci1. This would let the axi clock be disabled during runtime pm, so saves power a bit. Signed-off-by: Jisheng Zhang --- arch/arm/boot/dts/berlin2q.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 2f12048..a14c9e8 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -102,7 +102,8 @@ sdhci0: sdhci@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>; + clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; + clock-names = "core", "axi"; interrupts = ; status = "disabled"; }; @@ -110,7 +111,8 @@ sdhci1: sdhci@ab0800 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0800 0x200>; - clocks = <&chip_clk CLKID_SDIO1XIN>; + clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; + clock-names = "core", "axi"; interrupts = ; status = "disabled"; }; -- 2.6.1