From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752746AbbJQCWW (ORCPT ); Fri, 16 Oct 2015 22:22:22 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:42606 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751968AbbJQCWT (ORCPT ); Fri, 16 Oct 2015 22:22:19 -0400 From: Kishon Vijay Abraham I To: CC: , Subject: [PATCH 2/7] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs Date: Sat, 17 Oct 2015 07:52:13 +0530 Message-ID: <1445048538-4855-3-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1445048538-4855-1-git-send-email-kishon@ti.com> References: <1445048538-4855-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunfeng Yun add a DT binding documentation of usb3.0 phy for MT65xx SoCs from Mediatek. Acked-by: Rob Herring Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/phy-mt65xx-usb.txt | 68 ++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt new file mode 100644 index 0000000..00100cf --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt @@ -0,0 +1,68 @@ +mt65xx USB3.0 PHY binding +-------------------------- + +This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC. + +Required properties (controller (parent) node): + - compatible : should be "mediatek,mt8173-u3phy" + - reg : offset and length of register for phy, exclude port's + register. + - clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names + - clock-names : must contain + "u3phya_ref": for reference clock of usb3.0 analog phy. + +Required nodes : a sub-node is required for each port the controller + provides. Address range information including the usual + 'reg' property is used inside these nodes to describe + the controller's topology. + +Required properties (port (child) node): +- reg : address and length of the register set for the port. +- #phy-cells : should be 1 (See second example) + cell after port phandle is phy type from: + - PHY_TYPE_USB2 + - PHY_TYPE_USB3 + +Example: + +u3phy: usb-phy@11290000 { + compatible = "mediatek,mt8173-u3phy"; + reg = <0 0x11290000 0 0x800>; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; + clock-names = "u3phya_ref"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + phy_port0: port@11290800 { + reg = <0 0x11290800 0 0x800>; + #phy-cells = <1>; + status = "okay"; + }; + + phy_port1: port@11291000 { + reg = <0 0x11291000 0 0x800>; + #phy-cells = <1>; + status = "okay"; + }; +}; + +Specifying phy control of devices +--------------------------------- + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy port node and a device type; +phy-names for each port are optional. + +Example: + +#include + +usb30: usb@11270000 { + ... + phys = <&phy_port0 PHY_TYPE_USB3>; + phy-names = "usb3-0"; + ... +}; -- 1.7.9.5