From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754029AbbJSN2q (ORCPT ); Mon, 19 Oct 2015 09:28:46 -0400 Received: from eu-smtp-delivery-143.mimecast.com ([207.82.80.143]:34236 "EHLO eu-smtp-delivery-143.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753697AbbJSNZh (ORCPT ); Mon, 19 Oct 2015 09:25:37 -0400 From: "Suzuki K. Poulose" To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, christoffer.dall@linaro.org, steve.capper@linaro.org, Vladimir.Murzin@arm.com, james.morse@arm.com, andre.przywara@arm.com, ryan.arnold@linaro.org, aph@redhat.com, edward.nevill@linaro.org, dave.martin@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, "Suzuki K. Poulose" Subject: [PATCHv4 21/24] arm64: Add helper to decode register from instruction Date: Mon, 19 Oct 2015 14:24:58 +0100 Message-Id: <1445261101-22344-22-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1445261101-22344-1-git-send-email-suzuki.poulose@arm.com> References: <1445261101-22344-1-git-send-email-suzuki.poulose@arm.com> X-OriginalArrivalTime: 19 Oct 2015 13:25:27.0805 (UTC) FILETIME=[9E8C92D0:01D10A71] X-MC-Unique: uIgQ36jwRS-480rBCVvIVg-11 Content-Type: text/plain; charset=WINDOWS-1252 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id t9JDSrjj008071 Add a helper to extract the register field from a given instruction. Signed-off-by: Suzuki K. Poulose --- arch/arm64/include/asm/insn.h | 2 ++ arch/arm64/kernel/insn.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 30e50eb..6dea3bc 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -289,6 +289,8 @@ enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn); u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, u32 insn, u64 imm); +u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type, + u32 insn); u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr, enum aarch64_insn_branch_type type); u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr, diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index f341866..4286fed 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -388,6 +388,35 @@ u32 __kprobes aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, return insn; } +u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type, + u32 insn) +{ + int shift; + + switch (type) { + case AARCH64_INSN_REGTYPE_RT: + case AARCH64_INSN_REGTYPE_RD: + shift = 0; + break; + case AARCH64_INSN_REGTYPE_RN: + shift = 5; + break; + case AARCH64_INSN_REGTYPE_RT2: + case AARCH64_INSN_REGTYPE_RA: + shift = 10; + break; + case AARCH64_INSN_REGTYPE_RM: + shift = 16; + break; + default: + pr_err("%s: unknown register type encoding %d\n", __func__, + type); + return 0; + } + + return (insn >> shift) & GENMASK(4, 0); +} + static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type, u32 insn, enum aarch64_insn_register reg) -- 1.7.9.5