From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756391AbbJUUQV (ORCPT ); Wed, 21 Oct 2015 16:16:21 -0400 Received: from mga01.intel.com ([192.55.52.88]:20160 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756371AbbJUUQS (ORCPT ); Wed, 21 Oct 2015 16:16:18 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,178,1444719600"; d="scan'208";a="585560235" From: Andi Kleen To: peterz@infradead.org Cc: linux-kernel@vger.kernel.org, Andi Kleen Subject: [PATCH 2/3] x86, perf: Factor out BTS enable/disable functions Date: Wed, 21 Oct 2015 13:16:07 -0700 Message-Id: <1445458568-16956-2-git-send-email-andi@firstfloor.org> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1445458568-16956-1-git-send-email-andi@firstfloor.org> References: <1445458568-16956-1-git-send-email-andi@firstfloor.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andi Kleen Move BTS enable/disable into own functions. Used by the next patch. Signed-off-by: Andi Kleen --- arch/x86/kernel/cpu/perf_event_intel.c | 43 ++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 68a37b5..31323cc 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1457,20 +1457,39 @@ static __initconst const u64 slm_hw_cache_event_ids }, }; -/* - * Use from PMIs where the LBRs are already disabled. - */ -static void __intel_pmu_disable_all(void) +static inline void intel_pmu_maybe_disable_bts(void) { struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); - wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); - if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) intel_pmu_disable_bts(); else intel_bts_disable_local(); +} + +static inline void intel_pmu_maybe_enable_bts(void) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { + struct perf_event *event = + cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; + + if (WARN_ON_ONCE(!event)) + return; + + intel_pmu_enable_bts(event->hw.config); + } else + intel_bts_enable_local(); +} + +/* + * Use from PMIs where the LBRs are already disabled. + */ +static void __intel_pmu_disable_all(void) +{ + wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); + intel_pmu_maybe_disable_bts(); intel_pmu_pebs_disable_all(); } @@ -1488,17 +1507,7 @@ static void __intel_pmu_enable_all(int added, bool pmi) intel_pmu_lbr_enable_all(pmi); wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); - - if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { - struct perf_event *event = - cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; - - if (WARN_ON_ONCE(!event)) - return; - - intel_pmu_enable_bts(event->hw.config); - } else - intel_bts_enable_local(); + intel_pmu_maybe_enable_bts(); } static void intel_pmu_enable_all(int added) -- 2.4.3