From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753535AbbJWS3I (ORCPT ); Fri, 23 Oct 2015 14:29:08 -0400 Received: from mail-pa0-f53.google.com ([209.85.220.53]:36058 "EHLO mail-pa0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753488AbbJWS2g (ORCPT ); Fri, 23 Oct 2015 14:28:36 -0400 From: Douglas Anderson To: heiko@sntech.de, kishon@ti.com, johnyoun@synopsys.com, balbi@ti.com Cc: gregkh@linuxfoundation.org, lyz@rock-chips.com, wulf@rock-chips.com, Douglas Anderson , robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] ARM: dts: rockchip: Enable the USB phys as reset providers on rk3288 Date: Fri, 23 Oct 2015 11:28:10 -0700 Message-Id: <1445624891-31680-4-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.6.0.rc2.230.g3dd15c0 In-Reply-To: <1445624891-31680-1-git-send-email-dianders@chromium.org> References: <1445624891-31680-1-git-send-email-dianders@chromium.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As per the change to the rk3288 USB phy driver, we can now enable the PHYs as reset providers. Do so. Signed-off-by: Douglas Anderson --- arch/arm/boot/dts/rk3288.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 906e938..4f76805 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -778,6 +778,7 @@ usbphy0: usb-phy0 { #phy-cells = <0>; + #reset-cells = <0>; reg = <0x320>; clocks = <&cru SCLK_OTGPHY0>; clock-names = "phyclk"; @@ -785,6 +786,7 @@ usbphy1: usb-phy1 { #phy-cells = <0>; + #reset-cells = <0>; reg = <0x334>; clocks = <&cru SCLK_OTGPHY1>; clock-names = "phyclk"; @@ -792,6 +794,7 @@ usbphy2: usb-phy2 { #phy-cells = <0>; + #reset-cells = <0>; reg = <0x348>; clocks = <&cru SCLK_OTGPHY2>; clock-names = "phyclk"; -- 2.6.0.rc2.230.g3dd15c0