From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752123AbbJZQFE (ORCPT ); Mon, 26 Oct 2015 12:05:04 -0400 Received: from mail-bn1bbn0101.outbound.protection.outlook.com ([157.56.111.101]:17632 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751929AbbJZQEz (ORCPT ); Mon, 26 Oct 2015 12:04:55 -0400 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none;freescale.mail.onmicrosoft.com; dmarc=none action=none header.from=freescale.com; From: "J. German Rivera" To: , , , CC: , , , , , , , , , , , , , , "J. German Rivera" Subject: [PATCH 02/10] staging: fsl-mc: Added generic MSI support for FSL-MC devices Date: Mon, 26 Oct 2015 10:49:13 -0500 Message-ID: <1445874561-14761-3-git-send-email-German.Rivera@freescale.com> X-Mailer: git-send-email 2.3.3 In-Reply-To: <1445874561-14761-1-git-send-email-German.Rivera@freescale.com> References: <1445874561-14761-1-git-send-email-German.Rivera@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BY2FFO11OLC008;1:lzqdF1te2gVFOTxodXPZWq/ikCQdQdUBlGRwJerphj96aD3aS4hOPJCR3hHeyppVOWNWE1N8RFPpJB1+gEK9cCj6jlpMj5vkm3xk63lWUt6aH1FfTlghF1aBgWVJwddp84wX1lsoMd1xBQuEdde+vpviRuG9CrRt4syajgXRR4xUjp0NCQAJ3xCrYvm3DAoxo+HR1NkBpj/zlN07dGxQVL/ZePEK8kZ3h0Ll9oMoR5YiYOCS4rFOkfreHoFe144ouPeAM2ojDjdN3fR+udKBca1Dn/CV/6OZDX+e0xRDHpCNbc2U/OIn2TYfda0R+OlAMDKKhH3y7nzHV0A74N/5ja2xkgitz/qeKAgcJjqgzUewamqjfgq4cPNVqNMoOPh4ecN8UPRP5SkttwC9kzSZhA== X-Forefront-Antispam-Report: CIP:192.88.168.50;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(2970300002)(1110001)(1109001)(339900001)(199003)(189002)(105606002)(77096005)(189998001)(2950100001)(92566002)(5007970100001)(50226001)(97736004)(5003940100001)(11100500001)(4001430100002)(36756003)(81156007)(229853001)(5001770100001)(106466001)(87936001)(19580395003)(50466002)(5001920100001)(85426001)(86362001)(19580405001)(2201001)(107886002)(5001960100002)(104016004)(76176999)(50986999)(5008740100001)(6806005)(47776003)(48376002)(41533002);DIR:OUT;SFP:1102;SCL:1;SRVR:BY2PR03MB508;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;PTR:InfoDomainNonexistent;A:1;MX:3;LANG:en; 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Signed-off-by: J. German Rivera --- drivers/staging/fsl-mc/bus/Kconfig | 1 + drivers/staging/fsl-mc/bus/Makefile | 1 + drivers/staging/fsl-mc/bus/mc-msi.c | 278 ++++++++++++++++++++++++++++ drivers/staging/fsl-mc/include/mc-private.h | 17 ++ drivers/staging/fsl-mc/include/mc.h | 17 ++ 5 files changed, 314 insertions(+) create mode 100644 drivers/staging/fsl-mc/bus/mc-msi.c diff --git a/drivers/staging/fsl-mc/bus/Kconfig b/drivers/staging/fsl-mc/bus/Kconfig index 0d779d9..c498ac6 100644 --- a/drivers/staging/fsl-mc/bus/Kconfig +++ b/drivers/staging/fsl-mc/bus/Kconfig @@ -9,6 +9,7 @@ config FSL_MC_BUS tristate "Freescale Management Complex (MC) bus driver" depends on OF && ARM64 + select GENERIC_MSI_IRQ_DOMAIN help Driver to enable the bus infrastructure for the Freescale QorIQ Management Complex (fsl-mc). The fsl-mc is a hardware diff --git a/drivers/staging/fsl-mc/bus/Makefile b/drivers/staging/fsl-mc/bus/Makefile index 25433a9..a5f2ba4 100644 --- a/drivers/staging/fsl-mc/bus/Makefile +++ b/drivers/staging/fsl-mc/bus/Makefile @@ -13,5 +13,6 @@ mc-bus-driver-objs := mc-bus.o \ dpmng.o \ dprc-driver.o \ mc-allocator.o \ + mc-msi.o \ dpmcp.o \ dpbp.o diff --git a/drivers/staging/fsl-mc/bus/mc-msi.c b/drivers/staging/fsl-mc/bus/mc-msi.c new file mode 100644 index 0000000..dfe8016 --- /dev/null +++ b/drivers/staging/fsl-mc/bus/mc-msi.c @@ -0,0 +1,278 @@ +/* + * Freescale Management Complex (MC) bus driver MSI support + * + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Author: German Rivera + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "../include/mc-private.h" +#include +#include +#include +#include +#include +#include +#include "../include/mc-sys.h" +#include "dprc-cmd.h" + +static void fsl_mc_msi_set_desc(msi_alloc_info_t *arg, + struct msi_desc *desc) +{ + arg->desc = desc; + arg->hwirq = (irq_hw_number_t)desc->msi_attrib.entry_nr; +} + +static void fsl_mc_msi_update_dom_ops(struct msi_domain_info *info) +{ + struct msi_domain_ops *ops = info->ops; + + if (WARN_ON(!ops)) + return; + + if (!ops->set_desc) + ops->set_desc = fsl_mc_msi_set_desc; +} + +static void __fsl_mc_msi_write_msg(struct fsl_mc_device *mc_bus_dev, + struct fsl_mc_device_irq *mc_dev_irq) +{ + int error; + struct fsl_mc_device *owner_mc_dev = mc_dev_irq->mc_dev; + struct msi_desc *msi_desc = mc_dev_irq->msi_desc; + struct dprc_irq_cfg irq_cfg; + + /* + * msi_desc->msg.address is 0x0 when this function is invoked in + * the free_irq() code path. In this case, for the MC, we don't + * really need to "unprogram" the MSI, so we just return. + */ + if (msi_desc->msg.address_lo == 0x0 && msi_desc->msg.address_hi == 0x0) + return; + + if (WARN_ON(!owner_mc_dev)) + return; + + irq_cfg.paddr = ((u64)msi_desc->msg.address_hi << 32) | + msi_desc->msg.address_lo; + irq_cfg.val = msi_desc->msg.data; + irq_cfg.user_irq_id = msi_desc->irq; + + /* + * DPRCs and other objects use different commands to set up IRQs, + * so we have to differentiate them here. + */ + if (owner_mc_dev == mc_bus_dev) { + /* + * IRQ is for the mc_bus_dev's DPRC itself + */ + error = dprc_set_irq(mc_bus_dev->mc_io, + MC_CMD_FLAG_INTR_DIS | MC_CMD_FLAG_PRI, + mc_bus_dev->mc_handle, + mc_dev_irq->dev_irq_index, + &irq_cfg); + if (error < 0) { + dev_err(&owner_mc_dev->dev, + "dprc_set_irq() failed: %d\n", error); + } + } else { + error = dprc_set_obj_irq(mc_bus_dev->mc_io, + MC_CMD_FLAG_INTR_DIS | MC_CMD_FLAG_PRI, + mc_bus_dev->mc_handle, + owner_mc_dev->obj_desc.type, + owner_mc_dev->obj_desc.id, + mc_dev_irq->dev_irq_index, + &irq_cfg); + if (error < 0) { + dev_err(&owner_mc_dev->dev, + "dprc_obj_set_irq() failed: %d\n", error); + } + } +} + +/* + * NOTE: This function is invoked with interrupts disabled + */ +static void fsl_mc_msi_write_msg(struct irq_data *irq_data, + struct msi_msg *msg) +{ + struct msi_desc *msi_desc = irq_data_get_msi_desc(irq_data); + struct fsl_mc_device *mc_bus_dev = to_fsl_mc_device(msi_desc->dev); + struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); + struct fsl_mc_device_irq *mc_dev_irq = + &mc_bus->irq_resources[msi_desc->msi_attrib.entry_nr]; + + WARN_ON(mc_dev_irq->msi_desc != msi_desc); + msi_desc->msg = *msg; + + /* + * Program the MSI (paddr, value) pair in the device: + */ + __fsl_mc_msi_write_msg(mc_bus_dev, mc_dev_irq); +} + +static void fsl_mc_msi_update_chip_ops(struct msi_domain_info *info) +{ + struct irq_chip *chip = info->chip; + + if (WARN_ON((!chip))) + return; + + if (!chip->irq_write_msi_msg) + chip->irq_write_msi_msg = fsl_mc_msi_write_msg; +} + +/** + * fsl_mc_msi_create_irq_domain - Create a fsl-mc MSI interrupt domain + * @np: Optional device-tree node of the interrupt controller + * @info: MSI domain info + * @parent: Parent irq domain + * + * Updates the domain and chip ops and creates a fsl-mc MSI + * interrupt domain. + * + * Returns: + * A domain pointer or NULL in case of failure. + */ +struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, + struct msi_domain_info *info, + struct irq_domain *parent) +{ + struct irq_domain *domain; + + if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) + fsl_mc_msi_update_dom_ops(info); + if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) + fsl_mc_msi_update_chip_ops(info); + + domain = msi_create_irq_domain(fwnode, info, parent); + if (domain) + domain->bus_token = DOMAIN_BUS_FSL_MC_MSI; + + return domain; +} + +int fsl_mc_find_msi_domain(struct device_node *mc_of_node, + struct irq_domain **mc_msi_domain) +{ + struct device_node *msi_parent_node; + struct irq_domain *msi_domain; + + msi_parent_node = of_parse_phandle(mc_of_node, "msi-parent", 0); + if (!msi_parent_node) { + pr_err("msi-parent phandle missing for %s\n", + mc_of_node->full_name); + return -ENOENT; + } + + /* + * Look up the fsl-mc MSI domain: + */ + msi_domain = irq_find_matching_host(msi_parent_node, + DOMAIN_BUS_FSL_MC_MSI); + if (!msi_domain) { + pr_err("Unable to find fsl-mc MSI domain for %s\n", + mc_of_node->full_name); + + return -ENOENT; + } + + *mc_msi_domain = msi_domain; + return 0; +} + +static void fsl_mc_msi_free_descs(struct device *dev) +{ + struct msi_desc *desc, *tmp; + + list_for_each_entry_safe(desc, tmp, dev_to_msi_list(dev), list) { + list_del(&desc->list); + free_msi_entry(desc); + } +} + +static int fsl_mc_msi_alloc_descs(struct device *dev, unsigned int irq_count) + +{ + unsigned int i; + int error; + struct msi_desc *msi_desc; + + for (i = 0; i < irq_count; i++) { + msi_desc = alloc_msi_entry(dev); + if (!msi_desc) { + dev_err(dev, "Failed to allocate msi entry\n"); + error = -ENOMEM; + goto cleanup_msi_descs; + } + + msi_desc->msi_attrib.is_msix = 1; + msi_desc->msi_attrib.is_64 = 1; + msi_desc->msi_attrib.entry_nr = i; + msi_desc->nvec_used = 1; + INIT_LIST_HEAD(&msi_desc->list); + list_add_tail(&msi_desc->list, dev_to_msi_list(dev)); + } + + return 0; + +cleanup_msi_descs: + fsl_mc_msi_free_descs(dev); + return error; +} + +int fsl_mc_msi_domain_alloc_irqs(struct device *dev, + unsigned int irq_count) +{ + struct irq_domain *msi_domain; + int error; + + if (WARN_ON(!list_empty(dev_to_msi_list(dev)))) + return -EINVAL; + + error = fsl_mc_msi_alloc_descs(dev, irq_count); + if (error < 0) + return error; + + msi_domain = dev_get_msi_domain(dev); + if (WARN_ON(!msi_domain)) { + error = -EINVAL; + goto cleanup_msi_descs; + } + + /* + * NOTE: Calling this function will trigger the invocation of the + * its_fsl_mc_msi_prepare() callback + */ + error = msi_domain_alloc_irqs(msi_domain, dev, irq_count); + + if (error) { + dev_err(dev, "Failed to allocate IRQs\n"); + goto cleanup_msi_descs; + } + + return 0; + +cleanup_msi_descs: + fsl_mc_msi_free_descs(dev); + return error; +} + +void fsl_mc_msi_domain_free_irqs(struct device *dev) +{ + struct irq_domain *msi_domain; + + msi_domain = dev_get_msi_domain(dev); + if (WARN_ON(!msi_domain)) + return; + + msi_domain_free_irqs(msi_domain, dev); + + if (WARN_ON(list_empty(dev_to_msi_list(dev)))) + return; + + fsl_mc_msi_free_descs(dev); +} diff --git a/drivers/staging/fsl-mc/include/mc-private.h b/drivers/staging/fsl-mc/include/mc-private.h index 2c4cc79..3dabd003 100644 --- a/drivers/staging/fsl-mc/include/mc-private.h +++ b/drivers/staging/fsl-mc/include/mc-private.h @@ -26,6 +26,9 @@ strcmp(_obj_type, "dpmcp") == 0 || \ strcmp(_obj_type, "dpcon") == 0) +struct irq_domain; +struct msi_domain_info; + /** * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device * @root_mc_bus_dev: MC object device representing the root DPRC @@ -79,11 +82,13 @@ struct fsl_mc_resource_pool { * @resource_pools: array of resource pools (one pool per resource type) * for this MC bus. These resources represent allocatable entities * from the physical DPRC. + * @irq_resources: Pointer to array of IRQ objects for the IRQ pool * @scan_mutex: Serializes bus scanning */ struct fsl_mc_bus { struct fsl_mc_device mc_dev; struct fsl_mc_resource_pool resource_pools[FSL_MC_NUM_POOL_TYPES]; + struct fsl_mc_device_irq *irq_resources; struct mutex scan_mutex; /* serializes bus scanning */ }; @@ -116,4 +121,16 @@ int __must_check fsl_mc_resource_allocate(struct fsl_mc_bus *mc_bus, void fsl_mc_resource_free(struct fsl_mc_resource *resource); +struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, + struct msi_domain_info *info, + struct irq_domain *parent); + +int fsl_mc_find_msi_domain(struct device_node *mc_of_node, + struct irq_domain **mc_msi_domain); + +int fsl_mc_msi_domain_alloc_irqs(struct device *dev, + unsigned int irq_count); + +void fsl_mc_msi_domain_free_irqs(struct device *dev); + #endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/drivers/staging/fsl-mc/include/mc.h b/drivers/staging/fsl-mc/include/mc.h index a933291..1c1d6ae 100644 --- a/drivers/staging/fsl-mc/include/mc.h +++ b/drivers/staging/fsl-mc/include/mc.h @@ -104,6 +104,23 @@ struct fsl_mc_resource { }; /** + * struct fsl_mc_device_irq - MC object device message-based interrupt + * @msi_desc: pointer to MSI descriptor allocated by fsl_mc_msi_alloc_descs() + * @mc_dev: MC object device that owns this interrupt + * @dev_irq_index: device-relative IRQ index + * @resource: MC generic resource associated with the interrupt + */ +struct fsl_mc_device_irq { + struct msi_desc *msi_desc; + struct fsl_mc_device *mc_dev; + u8 dev_irq_index; + struct fsl_mc_resource resource; +}; + +#define to_fsl_mc_irq(_mc_resource) \ + container_of(_mc_resource, struct fsl_mc_device_irq, resource) + +/** * Bit masks for a MC object device (struct fsl_mc_device) flags */ #define FSL_MC_IS_DPRC 0x0001 -- 2.3.3