From: Ross Zwisler <ross.zwisler@linux.intel.com>
To: linux-kernel@vger.kernel.org
Cc: Ross Zwisler <ross.zwisler@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Dan Williams <dan.j.williams@intel.com>,
Ingo Molnar <mingo@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
linux-nvdimm@ml01.01.org, x86@kernel.org,
Dave Chinner <david@fromorbit.com>, Jan Kara <jack@suse.com>
Subject: [PATCH 1/2] pmem: add wb_cache_pmem() to the PMEM API
Date: Wed, 28 Oct 2015 16:09:35 -0600 [thread overview]
Message-ID: <1446070176-14568-2-git-send-email-ross.zwisler@linux.intel.com> (raw)
In-Reply-To: <1446070176-14568-1-git-send-email-ross.zwisler@linux.intel.com>
The function __arch_wb_cache_pmem() was already an internal implementation
detail of the x86 PMEM API, but this functionality needs to be exported as
part of the general PMEM API to handle the fsync/msync case for DAX mmaps.
Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com>
---
arch/x86/include/asm/pmem.h | 11 ++++++-----
include/linux/pmem.h | 22 +++++++++++++++++++++-
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/pmem.h b/arch/x86/include/asm/pmem.h
index d8ce3ec..6c7ade0 100644
--- a/arch/x86/include/asm/pmem.h
+++ b/arch/x86/include/asm/pmem.h
@@ -67,18 +67,19 @@ static inline void arch_wmb_pmem(void)
}
/**
- * __arch_wb_cache_pmem - write back a cache range with CLWB
+ * arch_wb_cache_pmem - write back a cache range with CLWB
* @vaddr: virtual start address
* @size: number of bytes to write back
*
* Write back a cache range using the CLWB (cache line write back)
* instruction. This function requires explicit ordering with an
- * arch_wmb_pmem() call. This API is internal to the x86 PMEM implementation.
+ * arch_wmb_pmem() call.
*/
-static inline void __arch_wb_cache_pmem(void *vaddr, size_t size)
+static inline void arch_wb_cache_pmem(void __pmem *addr, size_t size)
{
u16 x86_clflush_size = boot_cpu_data.x86_clflush_size;
unsigned long clflush_mask = x86_clflush_size - 1;
+ void *vaddr = (void __force *)addr;
void *vend = vaddr + size;
void *p;
@@ -115,7 +116,7 @@ static inline size_t arch_copy_from_iter_pmem(void __pmem *addr, size_t bytes,
len = copy_from_iter_nocache(vaddr, bytes, i);
if (__iter_needs_pmem_wb(i))
- __arch_wb_cache_pmem(vaddr, bytes);
+ arch_wb_cache_pmem(addr, bytes);
return len;
}
@@ -138,7 +139,7 @@ static inline void arch_clear_pmem(void __pmem *addr, size_t size)
else
memset(vaddr, 0, size);
- __arch_wb_cache_pmem(vaddr, size);
+ arch_wb_cache_pmem(addr, size);
}
static inline bool __arch_has_wmb_pmem(void)
diff --git a/include/linux/pmem.h b/include/linux/pmem.h
index 85f810b3..2cd5003 100644
--- a/include/linux/pmem.h
+++ b/include/linux/pmem.h
@@ -53,12 +53,18 @@ static inline void arch_clear_pmem(void __pmem *addr, size_t size)
{
BUG();
}
+
+static inline void arch_wb_cache_pmem(void __pmem *addr, size_t size)
+{
+ BUG();
+}
#endif
/*
* Architectures that define ARCH_HAS_PMEM_API must provide
* implementations for arch_memcpy_to_pmem(), arch_wmb_pmem(),
- * arch_copy_from_iter_pmem(), arch_clear_pmem() and arch_has_wmb_pmem().
+ * arch_copy_from_iter_pmem(), arch_clear_pmem(), arch_wb_cache_pmem()
+ * and arch_has_wmb_pmem().
*/
static inline void memcpy_from_pmem(void *dst, void __pmem const *src, size_t size)
{
@@ -202,4 +208,18 @@ static inline void clear_pmem(void __pmem *addr, size_t size)
else
default_clear_pmem(addr, size);
}
+
+/**
+ * wb_cache_pmem - write back processor cache for PMEM memory range
+ * @addr: virtual start address
+ * @size: number of bytes to write back
+ *
+ * Write back the processor cache range starting at 'addr' for 'size' bytes.
+ * This function requires explicit ordering with a wmb_pmem() call.
+ */
+static inline void wb_cache_pmem(void __pmem *addr, size_t size)
+{
+ if (arch_has_pmem_api())
+ arch_wb_cache_pmem(addr, size);
+}
#endif /* __PMEM_H__ */
--
2.1.0
next prev parent reply other threads:[~2015-10-28 22:10 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-28 22:09 [PATCH 0/2] "big hammer" for DAX msync/fsync correctness Ross Zwisler
2015-10-28 22:09 ` Ross Zwisler [this message]
2015-10-28 22:09 ` [PATCH 2/2] pmem: Add simple and slow fsync/msync support Ross Zwisler
2015-10-28 23:02 ` Dan Williams
2015-10-28 22:24 ` [PATCH 0/2] "big hammer" for DAX msync/fsync correctness Jeff Moyer
2015-10-28 22:49 ` Dan Williams
2015-10-28 22:51 ` Ross Zwisler
2015-11-05 23:59 ` Dan Williams
2015-11-06 8:06 ` Thomas Gleixner
2015-11-06 16:04 ` Dan Williams
2015-11-06 17:35 ` Thomas Gleixner
2015-11-06 23:17 ` Dan Williams
2015-11-07 0:51 ` H. Peter Anvin
2015-11-07 6:50 ` Thomas Gleixner
2015-11-07 8:12 ` Dan Williams
2015-11-07 8:38 ` Thomas Gleixner
2015-11-07 9:02 ` Dan Williams
2015-11-07 9:24 ` Thomas Gleixner
2015-11-06 20:25 ` H. Peter Anvin
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