From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031135AbbJ3MMi (ORCPT ); Fri, 30 Oct 2015 08:12:38 -0400 Received: from mail.skyhub.de ([78.46.96.112]:55752 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031000AbbJ3MLw (ORCPT ); Fri, 30 Oct 2015 08:11:52 -0400 From: Borislav Petkov To: Ingo Molnar Cc: LKML Subject: [PATCH 3/3] x86/cpu: Add CLZERO detection Date: Fri, 30 Oct 2015 13:11:39 +0100 Message-Id: <1446207099-24948-4-git-send-email-bp@alien8.de> X-Mailer: git-send-email 2.3.5 In-Reply-To: <1446207099-24948-1-git-send-email-bp@alien8.de> References: <1446207099-24948-1-git-send-email-bp@alien8.de> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wan Zongshun AMD Fam17h processors introduce support for the CLZERO instruction. It zeroes out the 64 byte cache line specified in RAX. Add the bit here to allow /proc/cpuinfo to list the feature. Boris: we're adding this as a separate ->x86_capability leaf because CPUID_80000008_EBX is going to contain more feature bits and it will fill out with time. Signed-off-by: Wan Zongshun Cc: Andy Lutomirski Cc: Denys Vlasenko Cc: "H. Peter Anvin" Cc: Huang Rui Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Tony Luck Cc: x86-ml Link: http://lkml.kernel.org/r/1446059010-28010-3-git-send-email-Aravind.Gopalakrishnan@amd.com [Wrap code in patch form, fix comments. ] Signed-off-by: Aravind Gopalakrishnan Signed-off-by: Borislav Petkov --- arch/x86/include/asm/cpufeature.h | 5 ++++- arch/x86/kernel/cpu/common.c | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 9727b3b48bd1..e4f8010f22e0 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -12,7 +12,7 @@ #include #endif -#define NCAPINTS 13 /* N 32-bit words worth of info */ +#define NCAPINTS 14 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* @@ -255,6 +255,9 @@ /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ +/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ +#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ + /* * BUG word(s) */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index de22ea7ff82f..4ddd780aeac9 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -670,6 +670,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) c->x86_virt_bits = (eax >> 8) & 0xff; c->x86_phys_bits = eax & 0xff; + c->x86_capability[13] = cpuid_ebx(0x80000008); } #ifdef CONFIG_X86_32 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) -- 2.3.5