From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753664AbbJaNRf (ORCPT ); Sat, 31 Oct 2015 09:17:35 -0400 Received: from mail-am1on0076.outbound.protection.outlook.com ([157.56.112.76]:42432 "EHLO emea01-am1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750903AbbJaNR0 (ORCPT ); Sat, 31 Oct 2015 09:17:26 -0400 Authentication-Results: spf=fail (sender IP is 212.179.42.66) smtp.mailfrom=ezchip.com; linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=none action=none header.from=ezchip.com; From: Noam Camus To: CC: , , , , Noam Camus , Daniel Lezcano , Rob Herring Subject: [PATCH v1 02/20] clocksource: Add NPS400 timers driver Date: Sat, 31 Oct 2015 15:15:09 +0200 Message-ID: <1446297327-16298-3-git-send-email-noamc@ezchip.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1446297327-16298-1-git-send-email-noamc@ezchip.com> References: <1446297327-16298-1-git-send-email-noamc@ezchip.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-11.0.0.1191-8.000.1202-21912.007 X-TM-AS-Result: No--17.545200-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;DB3FFO11OLC004;1:MHqjurZH0nEkplPKUlwcHWq2Tb/ayvIe9O6fu4OUMR9Xdaid2emfjqAQTlGPBcTgKd0biEFJVBVEejW12tL4kVQV7VObD6bvJFSEM8YpLLMIGz3Jt6t4bRTxtIr+b8ruHy+15f6uRnkVYYyWSxwCYbL85xUc4stLhVdAMqDZe8JGX8BWQVB6Qdrwxued0Fv535uROfTLl7eUqQhXbl+VEa77SytV8gkXNT6PHN1ntTL/bZXn40zBCHR2tcM4Zj980SXgoAjb9RnTfd84xR7D1ZioqmKTYFO6AqZ0Oj8Rnb0Hs0JpLMmEi/5cIjirJR4ajYW3OCZXKIBVOgtr3MZeTPZtL8zhXeEgUqpLbjLVzyTZgcnHDSr5laMYM2GCfZ2LTbU97hOKgJmi73d1msCfFw== X-Forefront-Antispam-Report: CIP:212.179.42.66;CTRY:IL;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(1110001)(1109001)(339900001)(199003)(189002)(229853001)(106466001)(105606002)(36756003)(5008740100001)(5003940100001)(104016004)(92566002)(76176999)(2351001)(50986999)(6806005)(77096005)(86362001)(2950100001)(85426001)(87936001)(5007970100001)(11100500001)(19580405001)(19580395003)(189998001)(5001920100001)(33646002)(5001970100001)(50466002)(47776003)(110136002)(50226001)(48376002)(49486002)(575784001)(2004002);DIR:OUT;SFP:1101;SCL:1;SRVR:DB5PR02MB1142;H:ezex10.ezchip.com;FPR:;SPF:Fail;PTR:ezmail.ezchip.com;A:1;MX:1;LANG:en; X-Microsoft-Exchange-Diagnostics: 1;DB5PR02MB1142;2:TJgxBXN3h9JQR7IGFPnKLSkAHl9yPP/uPeBb/yRoGFFWEXciJxC2aZekQWq8IwveCHG+j7gCn8OBidxIKRXAU4uheNmiBQotmMC0Pww6YhQGIhASs1FfbHdfTYXul8urFtD0kDtIj1y7DVYP9qQjuw1QxmZq/erGMhPcbnS7rB0=;3:hUyl5wG8MqzphaYo1wMUU8W1NCwce1B1aA05m9yyxUTx86Z2noRDs3hIX59OZyPYub3eaYRFPzNqKTsw64PeOQ1WudzSCZBtoXBC2tfOKBSH2gbJHzrTuSHY397mBJFnehF1ti34QUgoJCk0KZLn6AuZhlqG/pbkHuFGccwyyQO9LBuxFmnpcba2lfQbzOeO7X2rpHxJNjfuULtZoFEASP3/3emeVo45A1j0mm6WNVI=;25:sBacCukpO+j/HheYOJsGwiEJBpLfzXux+Ue/rdFymeFGUxJUst/JXVOnskLiot8k6L4ItrKr9wk6CccR66FwPfk1vs7pj2MYDVwE7VV9S2DuN4Z00kXA/C+0J8Pi0wFXoq97GQfZUCXRY0w1eZ7aICFviy/aRvmYrCeDdk5DRZyziTMk2R6Evbt2K/9MlW3DLNtB+8jdWPWyqlytoHfiRWD4GSe77c+btryfQqjIbviYvU0ujFaCFF9xJj8TN53e;20:Atnoo7O9+Bko+w0mqHtrA71L0Qw1UkkCeOrkhjETd9gkLvRLuoRHkYeGv8sJM2gmhKYRw6kAUCvsXOqCHbQBCHiBi9NntTB4jVv+xX8rQW4NDs/LzGTkzq98y5F1V4KA9M59sEXyEb2xnlPBODpk9VMAtbedmpBNuP1efhn1eB8= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DB5PR02MB1142; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(121898900299872); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(8121501046)(5005006)(520078)(3002001)(10201501046);SRVR:DB5PR02MB1142;BCL:0;PCL:0;RULEID:;SRVR:DB5PR02MB1142; X-Microsoft-Exchange-Diagnostics: 1;DB5PR02MB1142;4:vj2XXUz6qzwVUmHqyqMttPpgHYPzMWHYtGDOpxx10mZeD/JXKCnup/zMfiPo8jiqnsBxRPtpqCqsDpm/FsvRZXrkyP0dA2Kl1JCpYY6D/j1uzKIj5hu3tZ7z7WWizHUuZ3k56jpjWcw69tHm9McmBKdy3hC2NmAisdeVg9pv0NbO1vcqU3s3loY2C2lj4ZSYs5o7WCcHfcQxVXK+fclgBmznA3EOZ16dbbyYDVMcNcmV3Rh/dhgaAmSoJOcfOflW7jvvk+FS0qm1INVinVOaoHnf29yYwIFTDNvTYJNUye+j3ZxkewCgBI9Yz2AN1bitZj6qpR3u3Z7TIZXeG1m/qbde60rfvu5w/Ze68yqLcA4DAZIjz1zC5qVRdBSFzNKU X-Forefront-PRVS: 07467C4D33 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;DB5PR02MB1142;23:ZDJ8bzv+vsX9WoqSlvkizCgK3tkyGDqAa6cT5sZ3d?= =?us-ascii?Q?99QyMacFenL/Ucguz9hahj6ivZnSRH3TnWXmlsk2jPruvNo4+eTFihIyzTC2?= =?us-ascii?Q?my5e5aMV9VzspJtIhwUUw4OG0ekIXlcbWz5L7w91BA3tlwR3mzJK7B2FglMg?= =?us-ascii?Q?Z8VKhPq6xNRgfpWFnQrNmPyi13zLxdUpmwgxcsAr0hvoL9YwU+mYw3NJAW99?= =?us-ascii?Q?t1yCJsIYV5JWGv9pMKHmPK5tbvZEMECNFGloa9jV9x5iByBSgzVNz01FQunY?= =?us-ascii?Q?liENmM2A+fuGpUdqQf9335AUsoPFy8GO8aeNY2pDDpJMN5HXcONsyVosnIi8?= =?us-ascii?Q?hwMjId33WKQ56ArjW/KgCCNTX4VDQeesIWlxF/vYmOWTyNGr6ErSjzXxDRkk?= =?us-ascii?Q?mEV+eOYp/kVv9Q4O+AVlo+bzkXrwvantVc/nJvvbE2PiBV461r8RD/haXMUw?= =?us-ascii?Q?cLtD6JCMt0kwrdSGwvZsHfnMp8n6kjjp48EXD2+XSBBIwB+PoYDYanCfTDce?= =?us-ascii?Q?hGCURF5QETblrVYrspKNuRgc47LSW2Bei68QABZoxCvLP1uHUuFG39+QEBVj?= =?us-ascii?Q?VLxnrig5PKn4WF5z82bg0EAcp3JynFfkGqgOqS1BXy3Q0/kRg7rSSJYeapqS?= =?us-ascii?Q?ciptr5vdEXezCrJa8cmqg/etnjWmTnVmiEdhKhXO20yuUUnNnBEYxr28kgff?= =?us-ascii?Q?0FicPT6NO3ExWP3F0V47wj1DjvMK936jN+idqyKI2LNJL0hHJ1Qluk3F8o68?= =?us-ascii?Q?qdJzDrLBD3PcEEKXsSFd7KlVBkJ5cipA7Ed6+1z/B2yEr6lo2ohvBr9+gogZ?= =?us-ascii?Q?m+dZjXpLL0Y7DLahL6dw3ZXCyUoG5S92hn0W/c3Bu29b0jR/tc/RK7sbl7hE?= =?us-ascii?Q?GvvwgWhUdzhpcUV21wRgooxB4ZtRcgafU5J8duVDLFcx74UDt2fQ+FchVPxr?= =?us-ascii?Q?XXaRviraV36ue4DMNCjiWXxM+GFUC3oAR8UOgOmMiSWNwP/iUVSgg0NF9fT/?= =?us-ascii?Q?6jhXVYp45BjrArd1fs9lqnHVSSN9WqTI4IBO8YHnrlhdgey2famLYzKL5vbQ?= =?us-ascii?Q?vV3mHMThnFox6ZHGPlcffTaVAg624OssXLg5hrb0/7Z9jBX6w=3D=3D?= X-Microsoft-Exchange-Diagnostics: 1;DB5PR02MB1142;5:tJdSVPQKgM1qKuzSdvqaYMR5mlGgXnIx1UEsnEOe/eByFwMG+fZ0SGKAAYkewvnoQepweVwRyODfwFnmvOVWo43G3JouXXqsgRs5jv3lIL53oLX6TahhvLujsWLL3XpeeatvdhinFBYgHwlNQp9yIw==;24:/wqJ6XiSlvQ/i1pP54Oe6iB9HN4Uy0gsZLWfp2VQOoJIsRuwMHSqQPZTMksrllHmcVjeFDyfA+Qk5bcA3EmDnRfnTDVEvVbjIQokluVxVls=;20:0T12KjGyL85vBFLa5pAWXuS/WaLHCNOMpoSk4s2TTq3InBdh3jf4Gn2PlnUqrHylYkI3gl+Zx9m1oAGZwcnEXQ== SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: ezchip.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2015 13:17:21.4447 (UTC) X-MS-Exchange-CrossTenant-Id: 0fc16e0a-3cd3-4092-8b2f-0a42cff122c3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0fc16e0a-3cd3-4092-8b2f-0a42cff122c3;Ip=[212.179.42.66];Helo=[ezex10.ezchip.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR02MB1142 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Noam Camus Add internal tick generator which is shared by all cores. Each cluster of cores view it through dedicated address. This is used for SMP system where all CPUs synced by same clock source. Signed-off-by: Noam Camus Cc: Daniel Lezcano Cc: Rob Herring --- .../bindings/timer/ezchip,nps400-timer.txt | 11 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-nps.c | 103 ++++++++++++++++++++ 3 files changed, 115 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt create mode 100644 drivers/clocksource/timer-nps.c diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt new file mode 100644 index 0000000..c5102c2 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt @@ -0,0 +1,11 @@ +NPS Network Processor + +Required properties: + +- compatible : should be "ezchip,nps400-timer" + +Example: + +timer { + compatible = "ezchip,nps400-timer"; +}; diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 5c00863..28c17dc 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o +obj-$(CONFIG_ARC_PLAT_EZNPS) += timer-nps.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c new file mode 100644 index 0000000..83a0a9d --- /dev/null +++ b/drivers/clocksource/timer-nps.c @@ -0,0 +1,103 @@ +/* + * Copyright(c) 2015 EZchip Technologies. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in + * the file called "COPYING". + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NPS_MSU_TICK_LOW 0xC8 +#define NPS_CLUSTER_OFFSET 8 +#define NPS_CLUSTER_NUM 16 + +static u32 nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly; + +/* + * To get the value from the Global Timer Counter register proceed as follows: + * 1. Read the upper 32-bit timer counter register + * 2. Read the lower 32-bit timer counter register + * 3. Read the upper 32-bit timer counter register again. If the value is + * different to the 32-bit upper value read previously, go back to step 2. + * Otherwise the 64-bit timer counter value is correct. + */ +static cycle_t nps_clksrc_read(struct clocksource *clksrc) +{ + u64 counter; + u32 lower; + u32 upper, old_upper; + int cpu; + int cluster; + void *lower_p, *upper_p; + unsigned long flags; + + local_irq_save(flags); + cpu = smp_processor_id(); + cluster = cpu >> NPS_CLUSTER_OFFSET; + lower_p = (void *)nps_msu_reg_low_addr[cluster]; + upper_p = lower_p + 4; + local_irq_restore(flags); + + upper = ioread32be(upper_p); + do { + old_upper = upper; + lower = ioread32be(lower_p); + upper = ioread32be(upper_p); + } while (upper != old_upper); + + counter = upper; + counter <<= 32; + counter |= lower; + return (cycle_t)counter; +} + +static struct clocksource nps_counter = { + .name = "EZnps-tick", + .rating = 301, + .read = nps_clksrc_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void __init nps_setup_clocksource(struct device_node *node) +{ + struct clocksource *clksrc = &nps_counter; + unsigned long rate, dt_root; + int ret, cluster; + + for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++) + nps_msu_reg_low_addr[cluster] = + nps_host_reg((cluster << NPS_CLUSTER_OFFSET), + NPS_MSU_BLKID, NPS_MSU_TICK_LOW); + + dt_root = of_get_flat_dt_root(); + rate = (u32)of_get_flat_dt_prop(dt_root, "clock-frequency", NULL); + + ret = clocksource_register_hz(clksrc, rate); + if (ret) + pr_err("Couldn't register clock source.\n"); +} + +CLOCKSOURCE_OF_DECLARE(nps_400, "nps,400-timer", + nps_setup_clocksource); -- 1.7.1