From: Caesar Wang <wxt@rock-chips.com>
To: Heiko Stuebner <heiko@sntech.de>, Mark Brown <broonie@kernel.org>
Cc: Sonny Rao <sonnyrao@chromium.org>,
Dylan Reid <dgreid@chromium.org>,
Doug Anderson <dianders@chromium.org>,
Cheng-Yi Chiang <cychiang@chromium.org>,
linux-rockchip@lists.infradead.org,
Caesar Wang <wxt@rock-chips.com>,
Jaroslav Kysela <perex@perex.cz>,
alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org,
Takashi Iwai <tiwai@suse.com>,
Liam Girdwood <lgirdwood@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 0/5] Support more sample rates, let the rates normal work
Date: Tue, 3 Nov 2015 09:33:53 +0800 [thread overview]
Message-ID: <1446514438-13922-1-git-send-email-wxt@rock-chips.com> (raw)
That's seem the moment rockchip-codec driver other than 44100 and 48000 do not work.
Says the (max98090, rt5640).
----
As the chromeos reported issue:(https://chromium.googlesource.com/chromiumos/third_party/kernel/+/v3.14)
For detail:
In that bug we want to add 32000 to sound/soc/rockchip/rockchip_max98090.c rk_aif1_hw_params. However that does not work.
Previously, in https://chromium-review.googlesource.com/#/c/268398/ , rate 8000, 1600, 96000 were added.
However, those rates do not work. I got the same audio as 48000 when I run
aplay -D hw:0,0 /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 8000 -f S16_LE -c2
aplay -D hw:0,0 /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 16000 -f S16_LE -c2
aplay -D hw:0,0 /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 96000 -f S16_LE -c2
They all sound identical to
aplay -D hw:0,0 /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 48000 -f S16_LE -c2
Also, recording using
aplay -D hw:0,0 /usr/local/test.raw --rate 96000 -f S16_LE -c2 and examine the output we see it was recording using 48000.
Okay, let's add this series patchs to fix this issue.
arecord -D hw:0 -f S16_LE -c 2 --rate 96000 -d 5 foobar.wav
and
aplay -D hw:0 foobar.wav
Tested on veyron devices.
Changes in v1:
- change the subject and commit.
- remove the print message dev_dbg().
- Fix a subject missspell.
Caesar Wang (5):
ASoC: rockchip: i2s: Support to set the divider clock API
ASoC: rockchip-max98090: Allow more sample rates
ASoC: rockchip-rt5645: Allow more sample rates
ASoC: rockchip-max98090: Add the divider clock for cpu
ASoC: rockchip-rt5645: Add the divider clock for cpu
sound/soc/rockchip/rockchip_i2s.c | 27 +++++++++++++++++++++++++
sound/soc/rockchip/rockchip_max98090.c | 37 ++++++++++++++++++++++++++++++++++
sound/soc/rockchip/rockchip_rt5645.c | 37 ++++++++++++++++++++++++++++++++++
3 files changed, 101 insertions(+)
--
1.9.1
next reply other threads:[~2015-11-03 1:34 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-03 1:33 Caesar Wang [this message]
2015-11-03 1:33 ` [PATCH v1 1/5] ASoC: rockchip: i2s: Support to set the divider clock API Caesar Wang
2015-11-04 14:34 ` Mark Brown
[not found] ` <563AEF97.1080304@gmail.com>
2015-11-05 16:16 ` Mark Brown
2015-11-03 1:33 ` [PATCH v1 2/5] ASoC: rockchip-max98090: Allow more sample rates Caesar Wang
2015-11-03 1:33 ` [PATCH v1 3/5] ASoC: rockchip-rt5645: " Caesar Wang
2015-11-03 1:33 ` [PATCH v1 4/5] ASoC: rockchip-max98090: Add the divider clock for cpu Caesar Wang
2015-11-03 1:33 ` [PATCH v1 5/5] ASoC: rockchip-rt5645: " Caesar Wang
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