From: Jisheng Zhang <jszhang@marvell.com>
To: <sebastian.hesselbarth@gmail.com>, <robh+dt@kernel.org>,
<pawel.moll@arm.com>, <mark.rutland@arm.com>,
<ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>,
<linux@arm.linux.org.uk>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Jisheng Zhang <jszhang@marvell.com>
Subject: [PATCH v2 PART-RESEND 1/2] ARM: dts: berlin: correct BG2Q's sdhci2 2nd clock
Date: Mon, 16 Nov 2015 18:56:34 +0800 [thread overview]
Message-ID: <1447671395-8023-2-git-send-email-jszhang@marvell.com> (raw)
In-Reply-To: <1447671395-8023-1-git-send-email-jszhang@marvell.com>
The optional 2nd clock is CLKID_SDIO.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
arch/arm/boot/dts/berlin2q.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 155430a..145dd33 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -135,7 +135,7 @@
compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
+ clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>;
clock-names = "io", "core";
status = "disabled";
};
--
2.6.2
next prev parent reply other threads:[~2015-11-16 11:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-16 10:56 [PATCH v2 PART-RESEND 0/2] berlin sdhci clock clean up Jisheng Zhang
2015-11-16 10:56 ` Jisheng Zhang [this message]
2015-11-16 10:56 ` [PATCH v2 PART-RESEND 2/2] ARM: dts: berlin: add 2nd clock for BG2Q sdhci0 and sdhci1 Jisheng Zhang
2015-11-19 20:31 ` [PATCH v2 PART-RESEND 0/2] berlin sdhci clock clean up Sebastian Hesselbarth
2015-12-06 10:07 ` Sebastian Hesselbarth
2015-12-07 2:36 ` Jisheng Zhang
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