From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753538AbbKQMIc (ORCPT ); Tue, 17 Nov 2015 07:08:32 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:52918 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752146AbbKQMHE (ORCPT ); Tue, 17 Nov 2015 07:07:04 -0500 From: Chen Feng To: , , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH RFC 0/3] Add iommu support for hi6220 HiKey board Date: Tue, 17 Nov 2015 19:57:45 +0800 Message-ID: <1447761468-36952-1-git-send-email-puck.chen@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.184.163.62] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.564B183B.008D,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 46468fd3a22f29f48b988919d17be00c Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The patch sets add iommu support for Hi6220 SoC. Current testing and support board is Hikey which is one of 96boards. It is an arm64 open source board. For more information about this board, please access https://www.96boards.org. The Architecture of SMMU on Hi6220 SoC: +------------------------------------------------------------------+ | | | +---------+ +--------+ +-------------+ +-------+ | | | ADE | | ISP | | V/J codec | | G3D | | | +----|----+ +---|----+ +------|------+ +---|---| | | | | | | | | ---------v-----------v--------------v--------------v----- | | Media Bus | | --------------------------------|---------------|-------- | | | | | | +---v---------------v--------+ | | | SMMU | | | +----------|---------|-------+ | | | | | +--------------------------------------------|---------|-----------+ | | +------------v---------v-----------+ | DDRC | +----------------------------------+ Note: The media system share the same smmu IP to access DDR memory. And all media IP use the same page table. The hi6220 iommu driver also uses the iova api to manage an iova allocator to ensure that the caller get different iova address. The caller can use the follow sample code to map phy and iova address. eg: struct iommu_domain *domain = iommu_domain_alloc(bus); iommu_attach_device(domain, dev); struct iova_domain *iovad = (struct iova_domain *)m_dev->archdata.iommu; struct iova * t_iova = alloc_iova(iovad, size, limit_pfn, align); iommu_map(domain, t_iova->pfn_lo << 12, phy_addr, size, port); The patch sets are based on 4.4-RC1 Chen Feng (3): docs: iommu: Documentation for iommu in hi6220 SoC iommu/hisilicon: Add hi6220-SoC smmu driver arm64: dts: Add dts node for hi6220 smmu driver .../bindings/iommu/hisi,hi6220-iommu.txt | 32 ++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 13 + drivers/iommu/Kconfig | 11 + drivers/iommu/Makefile | 1 + drivers/iommu/hi6220_iommu.c | 492 +++++++++++++++++++++ 5 files changed, 549 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/hisi,hi6220-iommu.txt create mode 100644 drivers/iommu/hi6220_iommu.c -- 1.9.1