[PATCH 2/2] can: m_can: Add CAN clock generated by UPLLCK support

[Wenyou Yang <wenyou.yang@atmel.com>]

As said SAMA5D2 datasheet, it is recommended to use the CAN clock
at frequencies of 20, 40 or 80 MHz. To achieve these frequencies,
PMC GCK3 must select the UPLLCK(480 MHz) as source clock and
divide by 24, 12 or 6. In this patch the CAN clock at 20 MHz.

As it is configured through DT, it doesn't affect the M_CAN
without configuring CAN clock and its generated clock.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

 drivers/net/can/m_can/m_can.c |   16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index fd1caa0..2ca47db 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -269,6 +269,8 @@ enum m_can_mram_cfg {
 #define TX_BUF_XTD		BIT(30)
 #define TX_BUF_RTR		BIT(29)
 
+#define AT91_CAN_CLK_FREQ	20000000
+
 /* address offset and element number for each FIFO/Buffer in the Message RAM */
 struct mram_cfg {
 	u16 off;
@@ -1188,7 +1190,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
 	struct m_can_priv *priv;
 	struct resource *res;
 	void __iomem *addr;
-	struct clk *hclk, *cclk;
+	struct clk *hclk, *cclk, *upll_clk;
 	int irq, ret;
 
 	hclk = devm_clk_get(&pdev->dev, "hclk");
@@ -1198,6 +1200,18 @@ static int m_can_plat_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	upll_clk = devm_clk_get(&pdev->dev, "upllclk");
+	if (!IS_ERR(upll_clk)) {
+		ret = clk_set_parent(cclk, upll_clk);
+		if (!ret) {
+			ret = clk_set_rate(cclk, AT91_CAN_CLK_FREQ);
+			if (ret) {
+				dev_err(&pdev->dev, "failed to set gck\n");
+				return -ENODEV;
+			}
+		}
+	}
+
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
 	addr = devm_ioremap_resource(&pdev->dev, res);
 	irq = platform_get_irq_byname(pdev, "int0");
-- 
1.7.9.5