From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755147AbbKYIyR (ORCPT ); Wed, 25 Nov 2015 03:54:17 -0500 Received: from bhuna.collabora.co.uk ([46.235.227.227]:37337 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753866AbbKYIyQ (ORCPT ); Wed, 25 Nov 2015 03:54:16 -0500 From: Sjoerd Simons To: Mark Brown Cc: Jaroslav Kysela , alsa-devel@alsa-project.org, Heiko Stuebner , linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Takashi Iwai , Liam Girdwood , linux-arm-kernel@lists.infradead.org Subject: [PATCH] ASoC: rockchip: Fix incorrect VDW value for 24 bit Date: Wed, 25 Nov 2015 09:54:11 +0100 Message-Id: <1448441651-444-1-git-send-email-sjoerd.simons@collabora.co.uk> X-Mailer: git-send-email 2.6.2 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Correct valid data word register value for 24 bit data width. The bit value should be 10 (aka 0x2), not 0x10. This fixes playback of 24 bit audio. Signed-off-by: Sjoerd Simons --- sound/soc/rockchip/rockchip_spdif.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/rockchip/rockchip_spdif.h b/sound/soc/rockchip/rockchip_spdif.h index 07f86a2..921b409 100644 --- a/sound/soc/rockchip/rockchip_spdif.h +++ b/sound/soc/rockchip/rockchip_spdif.h @@ -28,9 +28,9 @@ #define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT) #define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT) -#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x00) -#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x01) -#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x10) +#define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0) +#define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1) +#define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2) /* * DMACR -- 2.6.2