From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752489AbbKZNsF (ORCPT ); Thu, 26 Nov 2015 08:48:05 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:40834 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751931AbbKZNrr (ORCPT ); Thu, 26 Nov 2015 08:47:47 -0500 X-AuditID: cbfee68f-f79666d0000076bb-a9-56570d7dfee1 From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, kgene@kernel.org, k.kozlowski@samsung.com Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC PATCH 03/15] ARM: dts: Add DMC bus node for Exynos3250 Date: Thu, 26 Nov 2015 22:47:27 +0900 Message-id: <1448545659-32287-4-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1448545659-32287-1-git-send-email-cw00.choi@samsung.com> References: <1448545659-32287-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKIsWRmVeSWpSXmKPExsWyRsSkQLeWNzzM4M9qVovrX56zWsw/co7V ov/NQlaLc69WMlq8fmFo0f/4NbPF2aY37BaXd81hs/jce4TRYsb5fUwWty/zWiy9fhHIaFzB ZjFh+loWi9a9R9gt2lZ/YHUQ8Fgzbw2jR0tzD5vH5b5eJo+Vy7+weWxa1cnm8e8Yu0ffllWM Hp83yQVwRHHZpKTmZJalFunbJXBlXHoxm7XgHk/F720PGRsY33B2MXJwSAiYSLR/ru5i5AQy xSQu3FvP1sXIxSEksIJRYtKjZ4wQCROJ5vcrWCASSxkl7t3+BFX1hVHi5uMJYFVsAloS+1/c YAOxRQRSJP7enM0IUsQscIhJ4sy7I0wgCWEBF4kn/5rBbBYBVYk5F+aC2bwCrhLn2pcwQ6yT k/iw5xE7iM0p4CZx6soksAVCQDWTP/aAbZYQ+Mgucf/9PDaIQQIS3yYfYoH4R1Zi0wGoOZIS B1fcYJnAKLyAkWEVo2hqQXJBcVJ6kbFecWJucWleul5yfu4mRmBsnf73rH8H490D1ocYBTgY lXh4C2zDwoRYE8uKK3MPMZoCbZjILCWanA+M4LySeENjMyMLUxNTYyNzSzMlcd6FUj+DhQTS E0tSs1NTC1KL4otKc1KLDzEycXBKNTC2fpBdtEtUZ5Pog3fx650mPtkt1beD7/bK90Vlnmdz Ahf0KfJ+//Xo5YTDDYdEMm4zv1P/MJvns1Dsp7UXFfvkhd6HBq3UefFYMD5u68QHglP9PaZd sSxIexq2gvHqGrGpdUlxzyRWSx+RWbev5vQsj2nTey/eS1vX/lDQbW7uF6Ydi9l881g3KLEU ZyQaajEXFScCAO4+Ce6oAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMIsWRmVeSWpSXmKPExsVy+t9jAd0a3vAwgzVLbSyuf3nOajH/yDlW i/43C1ktzr1ayWjx+oWhRf/j18wWZ5vesFtc3jWHzeJz7xFGixnn9zFZ3L7Ma7H0+kUgo3EF m8WE6WtZLFr3HmG3aFv9gdVBwGPNvDWMHi3NPWwel/t6mTxWLv/C5rFpVSebx79j7B59W1Yx enzeJBfAEdXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+TiE6Dr lpkD9ICSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCGMePSi9msBfd4Kn5v e8jYwPiGs4uRk0NCwESi+f0KFghbTOLCvfVsXYxcHEICSxkl7t3+BOV8YZS4+XgCI0gVm4CW xP4XN9hAbBGBFIm/N2czghQxCxxikjjz7ggTSEJYwEXiyb9mMJtFQFVizoW5YDavgKvEufYl zBDr5CQ+7HnEDmJzCrhJnLoyCWyBEFDN5I89bBMYeRcwMqxilEgtSC4oTkrPNcpLLdcrTswt Ls1L10vOz93ECI7gZ9I7GA/vcj/EKMDBqMTDW2AbFibEmlhWXJl7iFGCg1lJhPcWS3iYEG9K YmVValF+fFFpTmrxIUZToMMmMkuJJucDk0teSbyhsYmZkaWRuaGFkbG5kjjvhf1+YUIC6Ykl qdmpqQWpRTB9TBycUg2M4r9045qV2U7Xmk3Ve5a7ieXV4c3SLQvnuluzpGpekzgson31tPwi djOb9bfN1fhvJB/e5J1eqaDV4P5EkPmTrMWrh8K7C9MDjjPfdr25+VbUqwKmoBZ150PbWT/d bxecsO88X98V5dmn50hWWM/fce2jtpRPu++b71FufU9E62Q/ZttcOsOlxFKckWioxVxUnAgA Mb7PuvYCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the DMC (DRAM memory controller) bus node for Exynos3250 SoC. The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard SDRAM devices. The bus includes the OPP tables and the source clock for DMC block. Following list specifies the detailed relation between the clock and DMC block: - The source clock of DMC block : div_dmc Signed-off-by: Chanwoo Choi --- arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index be0bb32c2d8c..45809f83c628 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -700,6 +700,40 @@ clock-names = "ppmu"; status = "disabled"; }; + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_dmc CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <800000>; + }; + opp01 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <133000000>; + opp-microvolt = <800000>; + }; + opp03 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <800000>; + }; + opp04 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000>; + }; + }; }; }; -- 1.9.1