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x-ms-exchange-antispam-messagedata: R5tfa+RpuQpEm58VMFhiQMKQbgiotAsSdHswScLv5iB4blm1q0x7jrSmqiJiOwuLue7GJczCouA5X2h7eyHRZFrOpqYLS2VZj7QDOVG/Ki/l8fBhSjVxjEVQtcIFE3LV0eVxxprDK883xZck+FHV42AzEx5n0ehBUtMvCE1k+kBjr9GtGdo2eiAvZmjy4GIVWXK6m3MUwGqpRV0bRFRKFM7IACotpWuNF/1typc0fgwtVFJRFzj7Ikt2XKmhei83kfFN96VgJL0gLf//vt1ivFTcwVPtfHe2wyVBxdWaWkQEiwrxgfBU2zTw9t6c0e5UweLimnUV8F8cr4uM5cJhNuV+jSiZhKExs8MBxBwNe+wUZ6VhC7brWc5B7qtHngGHBWDvXotP9AW6eN8d42I9xp3jNL+OGHtctyLfMxHHV4a5mJCthoPd/6jp3mUOg/2ebOkdp3xTePtwDebgXXjWPqD3mpq/DcpJDEL3BDDqoNw= Content-Type: text/plain; charset="us-ascii" Content-ID: <8D67A0AB6DDE6549B9366E73092AA3CD@namprd11.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 2ad52947-c446-41ae-9f59-08d7f63c101d X-MS-Exchange-CrossTenant-originalarrivaltime: 12 May 2020 06:16:52.3332 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 0GPt2Yiz5THlRm+joYY2rNA1gmxGkanf+hah/HKpYQa95w6f84nR4Sddg4dmP7F1oOOHLMPUMqyFTppuDjRC59Ot5NI/VDJiKmfrcbV7QF8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4291 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Boris, Pratyush, I stripped case 2/, we'll not treat it for now. On Monday, May 11, 2020 12:27:12 PM EEST Boris Brezillon wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know th= e > content is safe >=20 > On Mon, 11 May 2020 09:00:35 +0000 >=20 > wrote: > > Hi, Pratyush, Boris, > >=20 > > On Friday, April 24, 2020 9:43:54 PM EEST Pratyush Yadav wrote: > > > This series adds support for octal DTR flashes in the spi-nor framewo= rk, > >=20 > > I'm still learning about this, but I can give you my 2 cents as of now,= to > > open the discussion. Enabling 2-2-2, 4-4-4, and 8-8-8 modes is dangerou= s > > because the flash may not recover from unexpected resets. Entering one = of > > these modes can be: > > 1/ volatile selectable, the device return to the 1-1-1 protocol after t= he > > next power-on. I guess this is conditioned by the optional RESET pin, b= ut > > I'll have to check. Also the flash can return to the 1-1-1 mode using t= he > > software reset or through writing to its Configuration Register, withou= t > > power-on or power- off. >=20 > My understanding is that there's no standard software reset procedure > that guarantees no conflict with existing 1S commands, so even the > software reset approach doesn't work here. >=20 The software reset procedure can't protect you from unexpected resets, but = the=20 hardware with its optional reset pin can. Pratyush to confirm. cut >=20 > > Not recovering from unexpected resets is unacceptable. One should alway= s > > prefer option 1/ and condition the entering in 2-2-2, 4-4-4 and 8-8-8 w= ith > > the presence of the optional RESET pin. >=20 > Totally agree with you on that one, but we know what happens in > practice... What I proposed is to condition the entering in the state-full modes with t= he=20 presence of the optional RESET pin. We would introduce an optional device t= ree=20 property for the RESET pin. If hardware doesn't implement the optional RESE= T#=20 signal, then we will not enter in the state-full modes. Cheers, ta