From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756637AbbLAPMq (ORCPT ); Tue, 1 Dec 2015 10:12:46 -0500 Received: from eu-smtp-delivery-143.mimecast.com ([207.82.80.143]:55775 "EHLO eu-smtp-delivery-143.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756560AbbLAPMn (ORCPT ); Tue, 1 Dec 2015 10:12:43 -0500 From: "Suzuki K. Poulose" To: linux-arm-kernel@lists.infradead.org Cc: marc.zyngier@arm.com, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will.deacon@arm.com, catalin.marinas@arm.com, "Suzuki K. Poulose" Subject: [PATCH v2 5/6] arm64: Add helper for extracting ASIDBits Date: Tue, 1 Dec 2015 15:12:10 +0000 Message-Id: <1448982731-17182-6-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1448982731-17182-1-git-send-email-suzuki.poulose@arm.com> References: <1448982731-17182-1-git-send-email-suzuki.poulose@arm.com> X-OriginalArrivalTime: 01 Dec 2015 15:12:37.0474 (UTC) FILETIME=[B6B17420:01D12C4A] X-MC-Unique: JA157YELRXahaB1Zi_7gSQ-9 Content-Type: text/plain; charset=WINDOWS-1252 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id tB1FCqT6028777 Add a helper to extract ASIDBits on the current cpu Cc: Will Deacon Cc: Mark Rutland Cc: Catalin Marinas Signed-off-by: Suzuki K. Poulose --- arch/arm64/mm/context.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index e87f53f..643bf4b 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -40,6 +40,28 @@ static cpumask_t tlb_flush_pending; #define ASID_FIRST_VERSION (1UL << asid_bits) #define NUM_USER_ASIDS ASID_FIRST_VERSION +/* Get the ASIDBits supported by the current CPU */ +static u32 get_cpu_asid_bits(void) +{ + u32 asid; + int fld = cpuid_feature_extract_field(read_cpuid(ID_AA64MMFR0_EL1), + ID_AA64MMFR0_ASID_SHIFT); + + switch (fld) { + default: + pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n", + smp_processor_id(), fld); + /* Fallthrough */ + case 0: + asid = 8; + break; + case 2: + asid = 16; + } + + return asid; +} + static void flush_context(unsigned int cpu) { int i; @@ -187,19 +209,7 @@ switch_mm_fastpath: static int asids_init(void) { - int fld = cpuid_feature_extract_field(read_cpuid(ID_AA64MMFR0_EL1), 4); - - switch (fld) { - default: - pr_warn("Unknown ASID size (%d); assuming 8-bit\n", fld); - /* Fallthrough */ - case 0: - asid_bits = 8; - break; - case 2: - asid_bits = 16; - } - + asid_bits = get_cpu_asid_bits(); /* If we end up with more CPUs than ASIDs, expect things to crash */ WARN_ON(NUM_USER_ASIDS < num_possible_cpus()); atomic64_set(&asid_generation, ASID_FIRST_VERSION); -- 1.7.9.5