From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932691AbbLCJar (ORCPT ); Thu, 3 Dec 2015 04:30:47 -0500 Received: from mga01.intel.com ([192.55.52.88]:19431 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757763AbbLCJaC (ORCPT ); Thu, 3 Dec 2015 04:30:02 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,377,1444719600"; d="scan'208";a="863722175" From: Heikki Krogerus To: Chanwoo Choi , Greg Kroah-Hartman Cc: MyungJoo Ham , David Cohen , Lu Baolu , Mathias Nyman , Felipe Balbi , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCHv2 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC Date: Thu, 3 Dec 2015 11:29:51 +0200 Message-Id: <1449134991-39095-3-git-send-email-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1449134991-39095-1-git-send-email-heikki.krogerus@linux.intel.com> References: <1449134991-39095-1-git-send-email-heikki.krogerus@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Intel Braswell/Cherrytrail has an internal mux that shares one USB port between USB Device Controller and xHCI. The same mux is found on several SOCs from Intel, but only on a few Cherrytrail based platforms the OS is expected to configure it. Normally BIOS takes care of it. The driver for the mux is an "extcon" driver. With this we only register the mux if it's detected. Suggested-by: Lu Baolu Signed-off-by: Heikki Krogerus --- drivers/usb/host/pci-quirks.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c index 26cb8c8..ee875e1 100644 --- a/drivers/usb/host/pci-quirks.c +++ b/drivers/usb/host/pci-quirks.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "pci-quirks.h" #include "xhci-ext-caps.h" @@ -1022,9 +1023,32 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev) writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); hc_init: - if (pdev->vendor == PCI_VENDOR_ID_INTEL) + if (pdev->vendor == PCI_VENDOR_ID_INTEL) { usb_enable_intel_xhci_ports(pdev); + /* + * Initialize the internal mux that shares a port between USB + * Device Controller and xHCI on platforms that have it. + */ +#define XHCI_INTEL_VENDOR_CAPS 192 +#define XHCI_INTEL_USB_MUX_OFFSET 0x80d8 + if (xhci_find_next_ext_cap(base, 0, XHCI_INTEL_VENDOR_CAPS)) { + struct intel_usb_mux *mux; + struct resource r; + + r.start = pci_resource_start(pdev, 0) + + XHCI_INTEL_USB_MUX_OFFSET; + r.end = r.start + 8; + r.flags = IORESOURCE_MEM; + + mux = intel_usb_mux_register(&pdev->dev, &r); + if (IS_ERR(mux) && PTR_ERR(mux) == -ENOTSUPP) + dev_dbg(&pdev->dev, "USB mux not supported\n"); + else if (IS_ERR(mux)) + dev_err(&pdev->dev, "failed to register mux\n"); + } + } + op_reg_base = base + XHCI_HC_LENGTH(readl(base)); /* Wait for the host controller to be ready before writing any -- 2.6.2