From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753020AbbLEHwm (ORCPT ); Sat, 5 Dec 2015 02:52:42 -0500 Received: from szxga03-in.huawei.com ([119.145.14.66]:34521 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752743AbbLEHwk (ORCPT ); Sat, 5 Dec 2015 02:52:40 -0500 From: yankejian To: , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board Date: Sat, 5 Dec 2015 15:56:58 +0800 Message-ID: <1449302218-54374-4-git-send-email-yankejian@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449302218-54374-1-git-send-email-yankejian@huawei.com> References: <1449302218-54374-1-git-send-email-yankejian@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.56629538.010B,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 10cd31e002eb32cdaee0be5475c6b50e Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon Hip05-D02 development board. Signed-off-by: yankejian --- .../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 6ac7c00..5318d78 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -187,6 +187,22 @@ Example: reg = <0xb0000000 0x10000>; }; +Hisilicon HiP05 PERISUB system controller + +Required properties: +- compatible : "hisilicon,peri-c-subctrl", "syscon"; +- reg : Register address and size + +The HiP05 PERISUB system controller is shared by peripheral controllers in +HiP05 Soc to implement some basic configurations. the peripheral + controllers include mdio, ddr, iic, uart, timer and so on. + +Example: + /* for HiP05 PCIe-SAS system */ + pcie_sas: system_controller@0xb0000000 { + compatible = "hisilicon,pcie-sas-subctrl", "syscon"; + reg = <0xb0000000 0x10000>; + }; ----------------------------------------------------------------------- Hisilicon CPU controller -- 1.9.1