From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753608AbbLIEKD (ORCPT ); Tue, 8 Dec 2015 23:10:03 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:42691 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753086AbbLIEIc (ORCPT ); Tue, 8 Dec 2015 23:08:32 -0500 X-AuditID: cbfee690-f79646d000001316-e6-5667a931e191 From: Chanwoo Choi To: myungjoo.ham@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Date: Wed, 09 Dec 2015 13:08:04 +0900 Message-id: <1449634091-1842-13-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> References: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHIsWRmVeSWpSXmKPExsWyRsSkWNdwZXqYQc8VHovrX56zWsw/co7V ov/NQlaLc69WMlq8fmFo0f/4NbPF2aY37BaXd81hs/jce4TRYsb5fUwW6zbeYre4fZnXYun1 i0wWtxtXsFlMmL6WxaJ17xF2i7bVH1gdBD3WzFvD6NHS3MPmcbmvl8lj56y77B4rl39h89i0 qpPN498xdo++LasYPT5vkgvgjOKySUnNySxLLdK3S+DKONW2laVggmpFf2teA+M36S5GTg4J AROJHVfnsUDYYhIX7q1n62Lk4hASWMEo8ebvHWaYov3fd7BDJGYxStx5uYAJwvnCKHHi/npW kCo2AS2J/S9usIHYIgLuEl/v7QYbxSzwhUmidfJ3sFHCAn4SMw/+YwexWQRUJd53bWQEsXkF XCUWrHzIDrFOTuLDnkdgNidQ/Mr2d2A1QgIuEseeNjFB1Pxll5jfwAYxR0Di2+RDQD9wAMVl JTYdgLpaUuLgihssExiFFzAyrGIUTS1ILihOSi8y0StOzC0uzUvXS87P3cQIjLbT/55N2MF4 74D1IUYBDkYlHt4LLulhQqyJZcWVuYcYTYE2TGSWEk3OB8Z0Xkm8obGZkYWpiamxkbmlmZI4 72upn8FCAumJJanZqakFqUXxRaU5qcWHGJk4OKUaGBWv92nu3bogpPiJ4KbEx3PVs8+cXmnG YFXmrZgkmKy5qUn5RUOr8++ndzxtuE3PLyqZ4c17bFvgvQi7lLMSS45ZcWubxcYmHklKuWus Eh6YbSP/ZNWBRLdr69/OEsqd7v/4xet39zY8jUgMPspQt1Mn7Z6Z2rGKMA7VlhP6YSePr6vz q69WUGIpzkg01GIuKk4EAGIXaVGxAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDIsWRmVeSWpSXmKPExsVy+t9jQV3DlelhBi/Xsllc//Kc1WL+kXOs Fv1vFrJanHu1ktHi9QtDi/7Hr5ktzja9Ybe4vGsOm8Xn3iOMFjPO72OyWLfxFrvF7cu8Fkuv X2SyuN24gs1iwvS1LBate4+wW7St/sDqIOixZt4aRo+W5h42j8t9vUweO2fdZfdYufwLm8em VZ1sHv+OsXv0bVnF6PF5k1wAZ1QDo01GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5 kkJeYm6qrZKLT4CuW2YO0CtKCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6jAzQQMIa xoxTbVtZCiaoVvS35jUwfpPuYuTkkBAwkdj/fQc7hC0mceHeerYuRi4OIYFZjBJ3Xi5ggnC+ MEqcuL+eFaSKTUBLYv+LG2wgtoiAu8TXe7vBOpgFvjBJtE7+zgySEBbwk5h58B/YWBYBVYn3 XRsZQWxeAVeJBSsfQq2Tk/iw5xGYzQkUv7L9HViNkICLxLGnTUwTGHkXMDKsYpRILUguKE5K zzXMSy3XK07MLS7NS9dLzs/dxAiO6WdSOxgP7nI/xCjAwajEw3vBJT1MiDWxrLgy9xCjBAez kgivVi1QiDclsbIqtSg/vqg0J7X4EKMp0GETmaVEk/OB6SavJN7Q2MTMyNLI3NDCyNhcSZy3 9lJkmJBAemJJanZqakFqEUwfEwenVAPjrOu3/yjw+on4rHkadu9TblUcg03spjed2RfUxTQm /GLk3ReyNpZpptj1PdcmGy7cuNtto/eN/bZnwz68OnVPKi12n/GUr/x8C0sPqnUn36koubpR +5e/iX5ku2na85LgNjcu+dPXHTqb3bRdPup9NZzFzbD84vnlNm8DZSN3TnR2dHHecsJViaU4 I9FQi7moOBEAsdMqQf8CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. Exynos3250 has following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK400 clock for MCUISP - ACLK266 clock for ISP - ACLK200 clock for FSYS - ACLK160 clock for LCD0 - ACLK100 clock for PERIL - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi --- arch/arm/boot/dts/exynos3250.dtsi | 160 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 7214c5e42150..46dee1951ec1 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -721,6 +721,166 @@ opp-microvolt = <875000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus_mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + }; + + bus_isp: bus_isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + }; + + bus_peril: bus_peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_mcuisp_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_isp_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_peril_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + }; }; }; -- 1.9.1