From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754240AbbLJRAt (ORCPT ); Thu, 10 Dec 2015 12:00:49 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:36052 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754136AbbLJRAq (ORCPT ); Thu, 10 Dec 2015 12:00:46 -0500 X-AuditID: cbfee61a-f79266d000003652-ff-5669afbcf775 From: Bartlomiej Zolnierkiewicz To: Thomas Abraham , Sylwester Nawrocki , Mike Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar , Krzysztof Kozlowski , Ben Gamari Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , Tobias Jakobi , Anand Moon , linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com Subject: [PATCH v5 5/7] clk: samsung: exynos5422/5800: fix cpu clock configuration data Date: Thu, 10 Dec 2015 17:58:47 +0100 Message-id: <1449766729-435-6-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1449766729-435-1-git-send-email-b.zolnierkie@samsung.com> References: <1449766729-435-1-git-send-email-b.zolnierkie@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsVy+t9jQd096zPDDJYc0rHYOGM9q8Ws+XdZ LK5/ec5q8f/Ra1aLN2/XMFm8fmFo0bvgKptF/+PXzBZfD69gtHjzcDOjxabH11gtLu+aw2bx ufcIo8WM8/uYLNZtvMVucfGUq8XhN+2sFh3LGC3aVn9gtVi16w+jxcavHg6iHu9vtLJ77Jx1 l91j06pONo871/aweWxeUu/x7xi7x5Z+oHDfllWMHmd+O3tsvzaP2ePzJrkA7igum5TUnMyy 1CJ9uwSujBW3n7EW3Jeo2Np6lqWB8aJIFyMnh4SAicTbr7dYIWwxiQv31rN1MXJxCAnMYpS4 e6CVFcL5xSjR8+orC0gVm4CVxMT2VYwgtojACSaJKZv8QIqYBV4zSxw9+JcJJCEsEClx+NgE sLEsAqoSb15MBGrm4OAVcJOY+4UdYpucxMljk8FKOAXcJbb+/coOUiIEVLL8afwERt4FjAyr GCVSC5ILipPScw3zUsv1ihNzi0vz0vWS83M3MYKj4pnUDsaDu9wPMQpwMCrx8L6QzgwTYk0s K67MPcQowcGsJMK7ZQZQiDclsbIqtSg/vqg0J7X4EKM0B4uSOG/tpcgwIYH0xJLU7NTUgtQi mCwTB6dUA6Pmy8vPuiYWPAm8PO1Baqfzgh7XrHeWSTcTdk0xOO/9af2+gCXXZq7cEyOsc+CG ScQL4Ua7n8+09pdlaST9ETPvqV61emsNvzXLd51qtgdMVkYnSkv+tJ45FMd/ec3LVzMECq3E 2mWqeetuZ294U+1mGmv8ee+ETbI7ClROTLfm3Lm9z1/q9kslluKMREMt5qLiRADWaBCbhgIA AA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix cpu clock configuration data for Exynos5422/5800 SoCs (they use higher PCLK_DBG divider values than Exynos5420 and support additional frequencies). Based on Hardkernel's kernel for ODROID-XU3 board. Cc: Tomasz Figa Cc: Mike Turquette Cc: Javier Martinez Canillas Cc: Thomas Abraham Acked-by: Sylwester Nawrocki Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 2a92546..837329d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { { 0 }, }; +static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { + { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, + { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, + { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, + { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, + { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, + { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 0 }, +}; + #define E5420_KFC_DIV(kpll, pclk, aclk) \ ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { + { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ { 1300000, E5420_KFC_DIV(3, 5, 2), }, { 1200000, E5420_KFC_DIV(3, 5, 2), }, { 1100000, E5420_KFC_DIV(3, 5, 2), }, @@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np, ARRAY_SIZE(exynos5800_gate_clks)); } - exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", - mout_cpu_p[0], mout_cpu_p[1], 0x200, - exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + if (soc == EXYNOS5420) { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + } else { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); + } exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", mout_kfc_p[0], mout_kfc_p[1], 0x28200, exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); -- 1.9.1